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MC9S08QG8CDTE Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc |
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MC9S08QG8CDTE Datasheet(HTML) 79 Page - Freescale Semiconductor, Inc |
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79 / 314 page  MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 77 Chapter 6 Parallel Input/Output Control This section explains software controls related to parallel input/output (I/O) and pin control. The MC9S08QG8 has two parallel I/O ports which include a total of 12 I/O pins, one output-only pin and one input-only pin. See Section Chapter 2, “External Signal Description,” for more information about pin assignments and external hardware considerations of these pins. Not all pins are available on all devices of the MC9S08QG8/4 Family; see Table 1-1 for the number of general-purpose pins available on your device. All of these I/O pins are shared with on-chip peripheral functions as shown in Table 2-2. The peripheral modules have priority over the I/Os so that when a peripheral is enabled, the I/O functions associated with the shared pins are disabled. After reset, the shared peripheral functions are disabled so that the pins are controlled by the I/O. All of the I/Os are configured as inputs (PTxDDn = 0) with pullup devices disabled (PTxPEn = 0), except for output-only pin PTA4 which defaults to the BKGD/MS pin. NOTE Not all general-purpose I/O pins are available on all packages. To avoid extra current drain from floating input pins, the user reset initialization routine in the application program must either enable on-chip pullup devices or change the direction of unconnected pins to outputs so the pins do not float. 6.1 Port Data and Data Direction Reading and writing of parallel I/Os is performed through the port data registers. The direction, either input or output, is controlled through the port data direction registers. The parallel I/O port function for an individual pin is illustrated in the block diagram shown in Figure 6-1. |
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