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78P2343JAT Datasheet(PDF) 15 Page - Teridian Semiconductor Corporation |
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78P2343JAT Datasheet(HTML) 15 Page - Teridian Semiconductor Corporation |
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15 / 37 page  78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator Page 15 of 37 2005 Teridian Semiconductor Corporation Rev 2.2 PIN DESCRIPTION (continued) CONTROL AND STATUS PINS NAME PIN TYPE DESCRIPTION MSL0 19 CIT Data-Rate Mode Selection: Low = E3 mode High = DS3 mode Float = STS-1 mode NOTE: Pin state is latched-in on rising-edge of PORB signal. Pin state is ignored after reset. MSL1 20 CIT Jitter Attenuator Mode Selection: Low = JAT in Receive path High = JAT in Transmit path Float = JAT is bypassed NOTE: Pin state is latched-in on rising-edge of PORB signal. Pin state is ignored after reset. PORB 14 A Chip Reset (active-low): Forces hardware reset on device. See description on Internal Power- on Reset for complete use of this pin. ENDECB 15 CID ENDEC Enable (active-low): Set high to disable internal ENDEC function. See description on B3ZS/HDB3 ENDEC with Line Code Violation Detect for complete use of this pin. NOTE: Relevant only when the REGEN bit is ‘0’. Pin must be held low when the REGEN bit is set. LBOx 5, 6 7 CIT Line Build-Out: Low = Used with 225ft or more of cable. High = Used with less than 225ft of cable. Float = Disable and power down transmitter. [TXEN=0; PDTX=1] NOTE: LBO control relevant only when the REGEN bit is ‘0’. Pin state sampled approximately once every 0.5ms. LPBKx 10, 11 12 CIT Loopback Enable: Low = Normal Operation High = Local Loopback. Transmitter looped back to Receiver Float = Remote Loopback. Receiver looped back to Transmitter NOTE: Relevant only when the REGEN bit is ‘0’. Pin state sampled approximately once every 0.5ms. INTRx 64, 63 62 CO Interrupt Flag: This pin is normally high when the INPOL bit is ‘0’ (default), and normally low when the INPOL bit is ‘1’. When an interrupt event occurs (as defined in the Interrupt Control Register description), the respective INTRx pin will change state. |
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