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78P2343JAT Datasheet(PDF) 6 Page - Teridian Semiconductor Corporation

Part No. 78P2343JAT
Description  3-port E3/DS3/STS-1 LIU with Jitter Attenuator
Download  37 Pages
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Maker  TERIDIAN [Teridian Semiconductor Corporation]
Homepage  http://www.teridian.com
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78P2343JAT Datasheet(HTML) 6 Page - Teridian Semiconductor Corporation

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78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
Page 6 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
Elastic Store Depth
To optimize the trade-off between data latency and
clock wander tolerance, the FIFO elastic store depth
can be selected through the serial port by writing to
the Jitter Attenuator Control Register (JACR) as
follows:
ESP[1:0]
bits
Elastic Store Depth
00
Pass-Through mode
01
16 UI
10
32 UI
11
64 UI (default)
The Elastic Store Depth selects the nominal FIFO
read pointer address. The total or maximum elastic
store depth is set to be twice as deep as the nominal
pointer address. The circular buffer length is always
twice as long as the nominal pointer address.
POWER-DOWN FUNCTION
Power-down
control
is
provided
to
allow
the
transceivers to be shut off individually. Transmit and
receive power-down can be set independently via
the PDTX and PDRX bits in the Mode Control
Register. Floating the respective LBOx pin can also
set PDTX for each channel. The Serial Control
Interface
and
Configuration
Registers
are
not
affected by power-down.
INTERNAL POWER-ON RESET
The 78P2343JAT includes on-chip Power-On Reset
(POR) function to ensure the serial-port registers are
initialized to known default states upon power-up.
Roughly 50us after Vcc reaches 2.4V at power up,
reset is released. This reset signal also sets all state
machines within the LIU to nominal operational
states. The internal reset signal is also brought out
to the PORB pin. This pin is a multi-function pin that
allows for the following:
1) Override the internal POR signal by driving in an
external active-low reset signal;
2) Monitor the state of the internal POR signal (for
test and debug only);
3) Add external capacitor to delay the release of
the internal power-on reset signal to allow the
MSL0 pin to stabilize prior to release of reset
(approximately 8
µs per nF added).
The
internal
resistance
of
the
PORB
pin
is
approximately 5k
Ω.
SERIAL CONTROL INTERFACE
The serial port controlled register allows a generic
controller to interface with the 78P2343JAT.
It is
used for mode settings, diagnostics and test, and
the retrieval of status and performance information.
The serial interface consists of four pins: Chip Select
(CS), Serial Clock (SCK), Serial Data In (SDI), and
Serial Data Out (SDO).
The CS pin initiates the
read and write operations. It can also be used to
select a particular device allowing SCK, SDI and
SDO to be bussed together. SCK is the clock input
that times the data on SDI and SDO. Data on SDI is
latched in on the rising-edge of SCK, and data on
SDO is clocked out using the falling edge of SCK.
SDI is used to insert mode, address, and register
data into the chip.
Address and Data information
are input least significant bit (LSB) first.
SDO is a tristate capable output. It is used to output
register data during a read operation. SDO output is
normally high impedance, and is enabled only
during the duration when register data is being
clocked out.
Read data is clocked out least
significant bit (LSB) first.
If SDI coming out of the micro-controller chip is also
tristate capable, SDI and SDO can be connected
together to simplify connections.
The maximum clock frequency for register access is
20MHz.
Note: To allow equipment to power up in a known
state, some register defaults are set by their
corresponding pin control at power-up.


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