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71M6511 Datasheet(PDF) 29 Page - Teridian Semiconductor Corporation |
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71M6511 Datasheet(HTML) 29 Page - Teridian Semiconductor Corporation |
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29 / 95 page  71M6511/71M6511H Single-Phase Energy Meter IC DATA SHEET AUGUST 2007 Page: 29 of 95 © 2005-2007 TERIDIAN Semiconductor Corporation V2.6 Interrupts The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and IEN2. External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71M6511/6511H, for example the CE, DIO, RTC EEPROM interface, comparators. Interrupt Overview: When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 51. Once interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction, "RETI". When a RETI instruction is performed, the processor will return to the instruction that would have been next when the interrupt occurred. When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following conditions are met: • No interrupt of equal or higher priority is already in progress. • An instruction is currently being executed and is not completed. • The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1. Interrupt response will require a varying amount of time depending on the state of the MPU when the interrupt occurs. If the MPU is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. In other cases, the response time depends on the current instruction. The fastest possible response to an interrupt is 7 machine cycles. This includes one machine cycle for detecting the interrupt and six cycles to perform the LCALL. Special Function Registers for Interrupts: Interrupt Enable 0 register (IE0) MSB LSB EAL WDT ES0 ET1 EX1 ET0 EX0 Table 34: The IEN0 Register Bit Symbol Function IEN0.7 EAL EAL=0 – disable all interrupts IEN0.6 WDT Not used for interrupt control IEN0.5 - IEN0.4 ES0 ES0=0 – disable serial channel 0 interrupt IEN0.3 ET1 ET1=0 – disable timer 1 overflow interrupt IEN0.2 EX1 EX1=0 – disable external interrupt 1 IEN0.1 ET0 ET0=0 – disable timer 0 overflow interrupt IEN0.0 EX0 EX0=0 – disable external interrupt 0 Table 35: The IEN0 Bit Functions |
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