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71M6531D Datasheet(PDF) 17 Page - Teridian Semiconductor Corporation

Part No. 71M6531D
Description  Energy Meter IC
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Maker  TERIDIAN [Teridian Semiconductor Corporation]
Homepage  http://www.teridian.com
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71M6531D Datasheet(HTML) 17 Page - Teridian Semiconductor Corporation

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FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
17
Hardware also provides a maximum pulse width feature. PLS_MAXWIDTH[7:0] selects a maximum nega-
tive pulse width to be Nmax updates according to the formula: Nmax = (2*PLS_MAXWIDTH+1). If
PLS_MAXWIDTH=255, no width checking is performed.
The WPULSE and RPULSE pulse generator outputs are available on DIO6 and DIO7, respectively. They
can also be output on OPT_TX (see OPT_TXE[1:0] for details).
1.3.4
Data RAM (XRAM)
The CE and MPU use a single general-purpose Data RAM (also referred to as XRAM). The Data RAM is
1024 32-bit words, shared between the CE and the MPU using a time-multiplex method. This reduces
MPU wait states when accessing CE data. When the MPU and CE are clocking at maximum frequency
(10 MHz), the DRAM will make up to four accesses during each 100 ns interval. These consist of two
MPU accesses, one CE access and one SPI access.
The Data RAM is 32 bits wide and uses an external multiplexer so as to appear byte-wide to the MPU.
The Data RAM hardware will convert an MPU byte write operation into a read-modify-write operation that
requires two Data RAM accesses. The second access is guaranteed to be available because the MPU
cannot access the XRAM on two consecutive instructions unless it is using the same address.
In addition to the reduction of wait states, this arrangement permits the MPU to easily use unneeded CE
data memory. Likewise, the amount of memory the CE uses is not limited by the size of a dedicated CE
data RAM.
1.3.5
CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle. Figure 6 shows the timing of the
samples taken during one multiplexer cycle.
The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers
PRE_SAMPS (0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integration time for each energy output
is:
PRE_SAMPS * SUM_CYCLES / 2520.6, where 2520.6 is the sample rate [Hz]
For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will establish 2100 samples per accumulation
cycle. PRE_SAMPS = 100 and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100
samples or 833 ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the
MPU that accumulated data are available.
Figure 6: Samples from Multiplexer Cycle
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle status information, such as sag data and the digitized input signal, is available to the MPU.
VA
IA
1/32768Hz =
30.518µs
13/32768Hz = 397µs
per mux cycle
IB
VB


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