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71M6531D Datasheet(PDF) 39 Page - Teridian Semiconductor Corporation
TERIDIAN [Teridian Semiconductor Corporation]
71M6531D Datasheet(HTML) 39 Page - Teridian Semiconductor Corporation
/ 115 page
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
© 2005-2009 TERIDIAN Semiconductor Corporation
For example, for a shift of -988 ppm, 4
⋅PREG + QREG = 262403 = 0x40103. PREG = 0x10040 and
QREG = 0x03. The default values of PREG and QREG, corresponding to zero adjustment, are 0x10000
and 0x0, respectively.
Default values for RTC_ADJ, PREG and QREG should be nominal values, at the center of the ad-
justment range. Extreme values (zero for example) can cause incorrect operation.
If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC
time as necessary.
The sub-second register of the RTC, SUBSEC, can be read by the MPU after the one second interrupt and
before reaching the next one second boundary. SUBSEC contains the count remaining, in 1/256 second
nominal clock periods, until the next one second boundary. When the RST_SUBSEC bit is written, the
SUBSEC counter is restarted. Reading and resetting the sub-second counter can be used as part of an
algorithm to accurately set the RTC.
The device includes an on-chip temperature sensor for determining the temperature of the bandgap re-
ference. If automatic temperature measurement is not performed by selecting CHOP_E = 00, the MPU
may request an alternate multiplexer frame containing the temperature sensor output by asserting
MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation re-
quired to offset the thermal drift in the system (see Section 3.4 Temperature Compensation).
The 71M6531D and 71M6532D include 128 KB of on-chip flash memory. The 71M6531F and 71M6532F
offer 256 KB of flash memory. The flash memory primarily contains MPU and CE program code. It also
contains images of the CE and MPU data in RAM, as well as of I/O RAM. On power-up, before enabling
the CE, the MPU copies these images to their respective locations.
The flash memory is segmented into individually erasable pages that contain 1024 bytes.
Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must
begin on a 1-KB boundary of the flash address space. The CE_LCTN[7:0] word defines which 1-KB
boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[7:0].
Flash Write Procedures
The MPU may write to the flash memory. This is one of the non-volatile storage options available to the
user in addition to external EEPROM.
FLSH_PWE (flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A)
between Flash and XRAM write operations. This bit must be cleared by the MPU after each byte write
operation. Write operations to this bit are inhibited when interrupts are enabled.
The MPU cannot write to flash while the CE is executing its code from flash. Two interrupts warn of colli-
sions between the MPU firmware and the CE timing. If a flash write operation is attempted while the CE
is busy, the flash write will not execute and the FW_COL0 interrupt will be issued. If a flash write is still in
progress when the CE would otherwise begin a code pass, the code pass is skipped, the write operation
is completed, and the FW_COL1 interrupt is issued.
The simplest flash write procedure disables the CE during the write operation and interpolates the meter-
ing measurements. However, this results in the loss of at least one second of data, because the CE has
to resynchronize with the mains voltage.
There is a brief guaranteed interval (typically 1/32768 s) between CE executions which occurs 2520 times
per second. The start of the interval can be detected with the CE_BUSY interrupt which occurs on the
falling edge of CE_BUSY (an internal signal measurable from TMUXOUT). However, this guaranteed idle
time (30.5 µs) is too short to write a byte which takes 42 µs or to erase a page of flash memory which
takes at least 20 ms. Some CE code has substantially longer idle times, but in those cases, firmware in-
terrupt latencies can easily consume the available write time. If a flash write fails in this scheme, the fail-
ure can be detected with the FWCOL0 or FWCOL1 interrupt and the write can be retried.
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