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71M6403 Datasheet(PDF) 19 Page - Teridian Semiconductor Corporation |
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71M6403 Datasheet(HTML) 19 Page - Teridian Semiconductor Corporation |
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19 / 75 page  71M6403 Electronic Trip Unit SEPTEMBER 2006 Page: 19 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 Port Registers: The I/O ports are controlled by Special Function Registers P0, P1, and P2. The contents of the SFR can be observed on corresponding pins on the chip. Writing a ‘1’ to any of the ports (see Table 9) causes the corresponding pin to be at high level (V3P3), and writing a ‘0’ causes the corresponding pin to be held at low level (GND). The data direction registers DIR0, DIR1, and DIR2 define individual pins as input or output pins (see the DIO section in On-Chip Resources for details. Register SFR Address R/W Description P0 0x80 R/W Register for port 0 read and write operations (pins DIO0…DIO7) DIR0 0xA2 R/W Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is an output. P1 0x90 R/W Register for port 1 read and write operations (pins DIO8…DIO15) DIR1 0x91 R/W Data direction register for port 1. P2 0xA0 R/W Register for port 2 read and write operations (pins DIO16…DIO21) DIR2 0xA1 R/W Data direction register for port 2. Table 9: Port Registers All four ports on the chip are bi-directional. Each of them consists of a Latch (SFR ‘P0’ to ‘P3’), an output driver, and an input buffer, therefore the MPU can output or read data through any of these ports if they are not used for alternate purposes. Special Function Registers Specific to the 71M6403 Table 10 shows the location and description of the 71M6403-specific SFRs. Register Alternative Name SFR Address R/W Description ERASE FLSH_ERASE 0x94 W This register is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle (default = 0x00). 0x55 – Initiate Flash Page Erase cycle. Must be preceded by a write to FLSH_PGADR @ SFR 0xB7. 0xAA – Initiate Flash Mass Erase cycle. Must be preceded by a write to FLSH_MEEN @ SFR 0xB2 and the debug port must be enabled. Any other pattern written to FLSH_ERASE will have no effect. PGADDR FLSH_PGADR 0xB7 R/W Flash Page Erase Address register containing the flash memory page address (page 0 thru 127) that will be erased during the Page Erase cycle (default = 0x00). Must be re-written for each new Page Erase cycle. EEDATA 0x9E R/W I 2C EEPROM interface data register EECTRL 0x9F R/W I 2C EEPROM interface control register. If the MPU wishes to write a byte of data to EEPROM, it places the data in EEDATA and then writes the ‘Transmit’ code to EECTRL. The write to EECTRL initiates the transmit sequence. See the section I2C Interface (EEPROM) for a description of the command and status bits available for EECTRL. |
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