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AD7171 Datasheet(PDF) 7 Page - Analog Devices

Part No. AD7171
Description  16-Bit Low Power Sigma-Delta ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7171 Datasheet(HTML) 7 Page - Analog Devices

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AD7171
Rev. 0 | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
SCLK
2
DOUT/RDY
3
AIN(+)
4
AIN(–)
5
REFIN(+)
10 NC
NOTES
1. NC = NO CONNECT.
2. CONNECT EXPOSED PAD TO GROUND.
9 PDRST
8VDD
7GND
6REFIN(–)
AD7171
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK has a Schmitt-triggered
input. The serial clock can be continuous with all data transmitted in a constant train of pulses. Alternatively, it
can be a noncontinuous clock with the information being transmitted from the ADC in smaller batches of data.
2
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. DOUT/RDY operates as a data ready
pin, going low to indicate the completion of a conversion. In addition, it functions as a serial data output pin to
access the data register of the ADC. Eight status bits accompany each data read. See
for further details.
The DOUT/
Figure 13
RDY falling edge can be used as an interrupt to a processor, indicating that new data is available. If
the data is not read after the conversion, the pin goes high before the next update occurs.
3
AIN(+)
Analog Input. AIN(+) is the positive terminal of the differential analog input pair AIN(+)/AIN(−).
4
AIN(−)
Analog Input. AIN(−) is the negative terminal of the differential analog input pair AIN(+)/AIN(−).
5
REFIN(+)
Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(–). The nominal
reference voltage (REFIN(+) – REFIN(−)) is 5 V, but the part can function with a reference of 0.5 V to VDD.
6
REFIN(−)
Negative Reference Input.
7
GND
Ground Reference Point.
8
VDD
Supply Voltage, 2.7 V to 5.25 V.
9
PDRST
Power-Down/Reset. When this pin is low, the ADC is placed in power-down mode. All the logic on the chip is
reset and the DOUT/RDY pin is tristated. When PDRST is high, the ADC is taken out of power-down mode. The
on-chip clock powers up and settles, and the ADC continuously converts. The internal clock requires 1 ms
approximately to power up.
10
NC
This pin should be connected to GND for correct operation.
EPAD
Connect the exposed pad to ground.


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