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## APW7098 Datasheet(PDF) 22 Page - Anpec Electronics Coropration

 Part No. APW7098 Description Two- Phase Buck PWM Controller with Integrated MOSFET Drivers Download 30 Pages Scroll/Zoom 100% Maker ANPEC [Anpec Electronics Coropration] Homepage http://www.anpec.com.tw Logo

## APW7098 Datasheet(HTML) 22 Page - Anpec Electronics Coropration

 22 / 30 page Copyright© ANPEC Electronics Corp.Rev. A.6 - Oct., 2009APW7098www.anpec.com.tw22Application Information (Cont.)PWM Compensation (Cont.)The pole and zero frequencies of the transfer functionare:Figure 8. Compensation NetworkC2R221FZ1××π×=() C3R3R121FZ2×+×π×=+×××π×=C2C1C2C1R221FP1C3R321FP2××π×=The closed loop gain of the converter can be written as:GAINLC X GAINPWM X GAINAMPFigure 9. shows the asymptotic plot of the closed loopconverter gain, and the following guidelines will help todesign the compensation network. Using the belowguidelines should give a compensation similar to thecurve plotted. A stable closed loop has a -20dB/ decadeslope and a phase margin greater than 45 degree.1. Choose a value for R1, usually between 1K and 5K.2. Select the desired zero crossover frequencyFO= (1/5 ~ 1/10) X FSWUse the following equation to calculate R2:3. Place the first zero FZ1 before the output LC filter doublepole frequency FLC.FZ1 = 0.75 X FLCCalculate the C2 by the equation:R1FFVVR2LCOINOSC××∆=4. Set the pole at the ESR zero frequency FESR:FP1 = FESRCalculate the C1 by the following equation:0.75FR221C2LC ×××π×=1FC2R22C2C1ESR −×××π×=5. Set the second pole FP2 at the half of the switchingfrequency and also set the second zero FZ2 at the output LCfilter double pole FLC. The compensation gain should notexceed the error amplifier open loop gain, check thecompensation gain at FP2 with the capabilities of theerror amplifier.FP2 = 0.5 X FSWFZ2 = FLCCombine the two equations will get the followingcomponent calculations:FLCFrequency(Hz)20log(R2/R1)20log(VIN/ΔVOSC)FZ1FZ2FP1FP2FESRPWM & Filter GainConverter GainCompensation GainVREFVOUTVCOMPR1R3C3R2C2C1FB1F2FR1R3LCSW−×=SWFR31C3××π=Figure 9. Converter Gain and FrequencyOutput Inductor SelectionThe duty cycle (D) of a buck converter is the function ofthe input voltage and output voltage. Once an output volt-age is fixed, it can be written as: