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PRELIMINARY
PSoC®5: CY8C52 Family Data Sheet
Document Number: 001-55034 Rev. *A
Page 3 of 85
1. Architectural Overview
Introducing the CY8C52 family of ultra low power, Flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit
PSoC®3 and 32-bit PSoC 5 platform. The CY8C52 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a very flexible analog subsystem, digital subsystem, routing, and I/O
enables a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
ANALOG SYSTEM
LCD Direct
Drive
CapSense
Temperature
Sensor
-
ADC
4 x
CMP
+
-
SYSTEM WIDE
RESOURCES
Program
Debug &
Trace
Boundary
Scan
Program&
Debug
8051or
Cortex M3 CPU
Interrupt
Controller
PHUB
DMA
Cache
Controller
SRAM
FLASH
EEPROM
EMIF
CPU SYSTEM
MEMORY SYSTEM
SYSTEM BUS
Digital Interconnect
Analog Interconnect
0. 5 to 5.5V
( Optional)
4- 33 MHz
(Optional)
Xtal
Osc
32.768 KHz
(Optional)
RTC
Timer
IMO
WDT
and
Wake
ILO
Clocking System
1.8V LDO
SMP
POR and
LVD
Sleep
Power
Power Management
System
USB
PHY
D+
D-
SAR
ADC
CAN
2.0
I2C
Master/
Slave
Universal Digital Block Array (24 x UDB)
4 x
Timer
Counter
PWM
FS USB
2.0
DIGITAL SYSTEM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UART
Logic
12- Bit PWM
I2C Slave
8- Bit SPI
12- Bit SPI
Logic
8- Bit
Timer
16- Bit PRS
UDB
8- Bit
Timer
Quadrature Decoder
16- Bit
PWM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
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