11 / 19 page
CY14E101LA
Document #: 001-42916 Rev. *B
Page 11 of 19
Note
15. CE or WE must be > VIH during address transitions.
Figure 5. SRAM Read Cycle #2: CE and OE Controlled [10, 14]
Figure 6. SRAM Write Cycle #1: WE Controlled [13, 14, 15]
Figure 7. SRAM Write Cycle #2: CE Controlled [13, 14, 15]
Address Valid
Address
Data Output
Output Data Valid
Standby
Active
High Impedance
CE
OE
I
CC
tHZCE
t
RC
tACE
tAA
t
LZCE
tDOE
t
LZOE
tPU
tPD
tHZOE
Data Output
Data Input
Input Data Valid
High Impedance
Address Valid
Address
Previous Data
t
WC
tSCE
tHA
tAW
t
PWE
tSA
tSD
t
HD
t
HZWE
t
LZWE
WE
CE
Data Output
Data Input
Input Data Valid
High Impedance
Address Valid
Address
tWC
t
SD
t
HD
WE
CE
tSA
tSCE
tHA
t
PWE
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