CY14B256KA
Document #: 001-55720 Rev. *A
Page 4 of 26
Device Operation
The CY14B256KA nvSRAM is made up of two functional
components paired in the same physical cell. These are a SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations
SRAM
read
and
write
operations
are
inhibited.
The
CY14B256KA supports infinite reads and writes similar to a
typical SRAM. In addition, it provides infinite RECALL operations
from the nonvolatile cells and up to 1 million STORE operations.
Refer the Truth Table For SRAM Operations on page 23 for a
complete description of read and write modes.
SRAM Read
The CY14B256KA performs a read cycle whenever CE and OE
are LOW, and WE and HSB are HIGH. The address specified on
pins A0-14 determines which of the 32,768 data bytes are
accessed. When the read is initiated by an address transition,
the outputs are valid after a delay of tAA (read cycle #1). If the
read is initiated by CE or OE, the outputs are valid at tACE or at
tDOE, whichever is later (read cycle #2). The data output
repeatedly responds to address changes within the tAA access
time without the need for transitions on any control input pins.
This remains valid until another address change or until CE or
OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins IO0-7 are
written into the memory if it is valid tSD before the end of a
WE-controlled write, or before the end of an CE-controlled write.
It is recommended that OE be kept HIGH during the entire write
cycle to avoid data bus contention on common I/O lines. If OE is
left LOW, internal circuitry turns off the output buffers tHZWE after
WE goes LOW.
AutoStore Operation
The CY14B256KA stores data to the nvSRAM using one of three
storage operations. These three operations are: Hardware
STORE, activated by the HSB; Software STORE, activated by
an address sequence; AutoStore, on device power down. The
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B256KA.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 6. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
may corrupt the data stored in nvSRAM.
Figure 2. AutoStore Mode
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 16 for the size of the VCAP. The voltage
on the VCAP pin is driven to VCC by a regulator on the chip. Place
INT
Output
Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
VSS
Ground
Ground for the Device. Must be connected to the ground of the system.
VCC
Power Supply Power Supply Inputs to the Device. 3.0V +20%, –10%
HSB
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation,
HSB is driven HIGH for short time with standard output high current.
VCAP
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Pin Definitions (continued)
Pin Name
I/O Type
Description
0.1uF
VCC
VCAP
WE
VCAP
VSS
VCC
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