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CY8C3444LTI-109 Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY8C3444LTI-109
Description  Programmable System-on-Chip (PSoC)
Download  99 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C3444LTI-109 Datasheet(HTML) 10 Page - Cypress Semiconductor

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PRELIMINARY
PSoC®3: CY8C34 Family Data Sheet
Document Number: 001-53304 Rev. *B
Page 10 of 99
Figure 2-6. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance
3. Pin Descriptions
IDAC0, IDAC2.
Low resistance output pin for high current DACs
(IDAC).
OpAmp0out, OpAmp2out.
High current output of uncommitted
opamp[4].
Extref0, Extref1.
External reference input to the analog system.
OpAmp0-, OpAmp2-.
Inverting input to uncommitted opamp.
OpAmp0+, OpAmp2+.
Noninverting
input
to
uncommitted
opamp.
GPIO.
General purpose I/O pin provides interfaces to the CPU,
digital peripherals, analog peripherals, interrupts, LCD segment
drive, and CapSense[4].
I2C0: SCL, I2C1: SCL.
I2C SCL line providing wake from sleep
on an address match. Any I/O pin can be used for I2C SCL if
wake from sleep is not required.
I2C0: SDA, I2C1: SDA.
I2C SDA line providing wake from sleep
on an address match. Any I/O pin can be used for I2C SDA if
wake from sleep is not required.
Ind.
Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi.
32.768 kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi.
4 to 33 MHz crystal oscillator pin.
nTRST.
Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
SIO.
Special I/O provides interfaces to the CPU, digital periph-
erals and interrupts with a programmable high threshold voltage,
analog comparator, high sink current, and high impedance state
when the device is unpowered.
SWDCK.
Serial Wire Debug Clock programming and debug port
connection.
SWDIO.
Serial Wire Debug Input and Output programming and
debug port connection.
SWV.
Single Wire Viewer debug output.
TCK.
JTAG Test Clock programming and debug port connection.
TDI.
JTAG
Test
Data
In
programming
and
debug
port
connection.
TDO.
JTAG Test Data Out programming and debug port
connection.
TMS.
JTAG Test Mode Select programming and debug port
connection.
USBIO, D+.
Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin. Pins are No Connect (NC) on
devices without USB.[2]
USBIO, D-.
Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin. Pins are No Connect (NC) on
devices without USB.[2]
Vboost.
Power sense connection to boost pump.
Vbat.
Battery supply to boost pump.
Vcca.
Output of analog core regulator and input to analog core.
Requires a 1 µF capacitor to Vssa. Regulator output not for
external use.
Vccd.
Output of digital core regulator and input to digital core.
Requires a capacitor from each Vccd pin to Vssd; see Power
System on page 25. Regulator output not for external use.
Vdda.
Supply for all analog peripherals and analog core
regulator. Vdda must be the highest voltage present on the
VDDD
VSSD
VDDA
VSSA
VSSD
Plane
VSSA
Plane
Note
4. GPIOs with OpAmp outputs are not recommended for use with CapSense.
[+] Feedback


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