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DS2482S-800+TR Datasheet(PDF) 3 Page - Maxim Integrated Products |
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DS2482S-800+TR Datasheet(HTML) 3 Page - Maxim Integrated Products |
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3 / 23 page  DS2482-800: Eight-Channel 1-Wire Master 3 of 23 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Standard 60 64 68 Write 0 Low Time tW0L Overdrive 7.1 7.5 7.9 µs Standard 5.0 5.3 5.6 Write 0 Recovery Time tREC0 Overdrive 2.8 3.0 3.2 µs Standard 570 600 630 Reset Low Time tRSTL Overdrive 68.4 72 75.6 µs Standard 66.5 70 73.5 Presence-Detect Sample Time tMSP Overdrive 7.1 7.5 7.9 µs Standard 7.6 8 8.4 Sampling for Short and Interrupt tSI Overdrive 0.7 0.75 0.8 µs Standard 554.8 584 613.2 Reset High Time tRSTH Overdrive 70.3 74 77.7 µs I²C-Pins (Note 7) See Figure 9 VCC = 2.9V to 3.7V 0.25 × VCC LOW Level Input Voltage VIL VCC = 4.5V to 5.5V -0.5 0.22 × VCC V HIGH Level Input Voltage VIH 0.7 × VCC VCC + 0.5V V Hysteresis of Schmitt Trigger Inputs Vhys 0.05 × VCC V LOW Level Output Voltage at 3mA Sink Current VOL 0.4 V Output Fall Time from VIhmin to VILmax with a Bus Capacitance from 10pF to 400pF tof 60 250 ns Pulse Width of Spikes that are Suppressed by the Input Filter tSP SDA and SCL pins only 50 ns Input Current Each I/O Pin with an Input Voltage Between 0.1VCCmax and 0.9VCCmax Ii (Notes 8, 9) -10 10 µA Input Capacitance Ci (Note 8) 10 pF SCL Clock Frequency fSCL 0 400 kHz Hold Time (Repeated) START Condition. After this Period, the First Clock Pulse is Generated. tHD:STA 0.6 µs LOW Period of the SCL Clock tLOW 1.3 µs HIGH Period of the SCL Clock tHIGH 0.6 µs Setup Time for a Repeated START Condition tSU:STA 0.6 µs Data Hold Time tHD:DAT (Notes 10, 11) 0.9 µs Data Setup Time tSU:DAT (Note 12) 250 ns Setup Time for STOP Condition tSU:STO 0.6 µs Bus Free Time Between a STOP and START Condition tBUF 1.3 µs Capacitive Load for Each Bus Line Cb (Note 13) 400 pF Oscillator Warm-Up Time tOSCWUP (Note 14) 100 µs |
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Similar Description - DS2482S-800+TR |
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