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LY61L1024JL Datasheet(PDF) 6 Page - Lyontek Inc. |
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LY61L1024JL Datasheet(HTML) 6 Page - Lyontek Inc. |
6 / 14 page LY61L1024 Rev. 2.2 128K X 8 BIT HIGH SPEED CMOS SRAM Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 ® AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE LY61L1024-10 LY61L1024-12 LY61L1024-15 PARAMETER SYM. MIN. MAX. MIN. MAX. MIN. MAX. UNIT Read Cycle Time tRC 10 - 12 - 15 - ns Address Access Time tAA - 10 - 12 - 15 ns Chip Enable Access Time tACE - 10 - 12 - 15 ns Output Enable Access Time tOE - 5 - 6 - 7 ns Chip Enable to Output in Low-Z tCLZ* 2 - 3 - 4 - ns Output Enable to Output in Low-Z tOLZ* 0 - 0 - 0 - ns Chip Disable to Output in High-Z tCHZ* - 5 - 6 - 7 ns Output Disable to Output in High-Z tOHZ* - 5 - 6 - 7 ns Output Hold from Address Change tOH 3 - 3 - 3 - ns (2) WRITE CYCLE LY61L1024-10 LY61L1024-12 LY61L1024-15 PARAMETER SYM. MIN. MAX. MIN. MAX. MIN. MAX. UNIT Write Cycle Time tWC 10 - 12 - 15 - ns Address Valid to End of Write tAW 8 - 10 - 12 - ns Chip Enable to End of Write tCW 8 - 10 - 12 - ns Address Set-up Time tAS 0 - 0 - 0 - ns Write Pulse Width tWP 8 - 9 - 10 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Data to Write Time Overlap tDW 6 - 7 - 8 - ns Data Hold from End of Write Time tDH 0 - 0 - 0 - ns Output Active from End of Write tOW* 2 - 3 - 4 - ns Write to Output in High-Z tWHZ* - 6 - 7 - 8 ns *These parameters are guaranteed by device characterization, but not production tested. |
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