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S-8365 Datasheet(PDF) 22 Page - Seiko Instruments Inc

Part No. S-8365
Description  STEP-UP, SUPER-SMALL PACKAGE, 1.2 MHz PWM CONTROL or PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLER
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Maker  SII [Seiko Instruments Inc]
Homepage  http://www.sii.co.jp
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S-8365 Datasheet(HTML) 22 Page - Seiko Instruments Inc

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STEP-UP, SUPER-SMALL PACKAGE, 1.2 MHz PWM CONTROL or PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLER
S-8365/8366 Series
Rev.1.1_00
Seiko Instruments Inc.
22
5. External transistor
A bipolar (NPN) or enhanced (Nch) MOS FET transistor can be used as an external transistor.
5.1 Bipolar NPN type
The driving ability to increase output current by using a bipolar transistor is determined based on the hFE value
and Rb value of the bipolar transistor. Figure 19 shows the peripheral circuit.
Nch
Pch
VDD
IPK
EXT
Cb
2200 pF
Rb
1 k
Figure 19 External Transistor Peripheral Circuit
The recommended Rb value is around 1 k
Ω. Calculate the required base current (Ib) based on the hFE value of
the bipolar transistor by using Ib =
IPK
hFE , and then select an Rb value smaller than that determined using:
Rb =
VDD
− 0.7
Ib
0.4
IEXTH
Smaller Rb values increase the output current, but decrease the efficiency. Actually, the current might flow on
pulses or the VDD or VSS voltage might drop due to wiring resistance, so determine the optimum value based on
experimentation.
Inserting a speed-up capacitor (Cb) in parallel with the Rb resistor as shown in Figure 19 reduces switching loss
and increases efficiency.
Select a speed-up capacitor for which the Cb value satisfies Cb
1
2
× π × Rb × fOSC × 0.7
.
Actually, however, the optimum Cb value varies depending on the characteristics of the bipolar transistor used,
so determine the optimum value based on experimentation.
5.2 Enhanced MOS FET type
Use an Nch power MOS FET. A MOS FET that has low ON-resistance (RON) and input capacitance (CISS) is
ideal for gaining efficiency. The ON-resistance and input capacitance generally have a tradeoff relationship.
ON-resistance is efficient in the range where the output current is high with relatively low frequency switching,
and input capacitance is efficient in the range where the output current is medium to low with high frequency
switching. Therefore, select a MOS FET for which the ON-resistance and input capacitance are optimum under
your usage conditions.
The input voltage (VDD) is supplied as the gate voltage of a MOS FET, so select a MOS FET for which the gate
withstand voltage is higher than the maximum value used for the input voltage, and for which the drain
withstand voltage is greater than or equal to the output voltage (VOUT) + the forward voltage of the diode (VD).
If a MOS FET for which the threshold value is near the UVLO detection voltage is used, a high current flows
upon power-on, and, in the worst case, the output voltage might not increase and the timer latch type
short-circuit protection circuit might operate. Therefore, select a MOS FET for which the threshold value is
sufficiently lower than the UVLO detection voltage.


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