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ATmega8A Datasheet(PDF) 69 Page - ATMEL Corporation |
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ATmega8A Datasheet(HTML) 69 Page - ATMEL Corporation |
69 / 307 page 69 8159C–AVR–07/09 ATmega8A 13.1.3 GIFR – General Interrupt Flag Register • Bit 7 – INTF1: External Interrupt Flag 1 When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I- bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT1 is configured as a level interrupt. • Bit 6 – INTF0: External Interrupt Flag 0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I- bit in SREG and the INT0 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. Bit 7654 321 0 INTF1 INTF0 – – – – – –GIFR Read/Write R/W R/W RRR RRR Initial Value 0000 000 0 |
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