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ATtiny48-MU Datasheet(PDF) 5 Page - ATMEL Corporation |
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ATtiny48-MU Datasheet(HTML) 5 Page - ATMEL Corporation |
5 / 266 page 5 8008C–AVR–03/09 ATtiny48/88 2. Overview The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. PORT C (8) PORT B (8) PORT D (8) 16bit T/C 1 8bit T/C 0 A/D Conv. Internal Bandgap Analog Comp. SPI TWI SRAM Flash EEPROM Watchdog Oscillator Watchdog Timer Oscillator Circuits / Clock Generation Power Supervision POR / BOD & RESET Program Logic debugWIRE 2 PA[0..3] (in TQFP and MLF) PC[0..7] PB[0..7] PD[0..7] 6 RESET CLKI CPU PORT A (4) |
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