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R5F213J5ANNP Datasheet(PDF) 5 Page - Renesas Technology Corp |
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R5F213J5ANNP Datasheet(HTML) 5 Page - Renesas Technology Corp |
5 / 56 page R8C/3JA Group 1. Overview REJ03B0263-0110 Rev.1.10 Sep 30, 2009 Page 5 of 54 1.3 Block Diagram Figure 1.2 shows a Block Diagram. Figure 1.2 Block Diagram D/A converter (8 bits × 2) R8C CPU core Memory ROM (1) RAM (2) Multiplier R0H R0L R1H R2 R3 R1L A0 A1 FB SB USP ISP INTB PC FLG I/O ports Notes: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. 8 Port P1 5 Port P3 5 1 Port P4 6 Port P0 6 Port P2 System clock generation circuit XIN-XOUT Low-speed on-chip oscillator XCIN-XCOUT Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 bits × 2) Timer RE (8 bits × 1) UART or clock synchronous serial I/O (8 bits × 3) I2C bus or SSU (8 bits × 1) Peripheral functions Watchdog timer (14 bits) A/D converter (10 bits × 10 channels) LIN module Comparator B Voltage detection circuit Comparator A DTC 1 Port P6 Low-speed on-chip oscillator for watchdog timer |
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