6

AT88SC0104C

2021KS–SMEM–10/09

Figure 3.

Bus Timing for 2 wire communications: SCL: Serial Clock, SDA – Serial Data I/O

SCL

SDA IN

SDA OUT

t

F

t

HIGH

t

LOW

t

LOW

t

R

t

AA

t

DH

t

BUF

t

SU.STO

t

SU.DAT

t

HD.DAT

t

HD.STA

t

SU.STA

Figure 4.

Write Cycle Timing: SCL: Serial Clock, SDA – Serial Data I/O

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA

Note

:

clear/write cycle.