8

AT88SC0204CA

5202ES–CRYPT–08/09

Figure 5.

Write Cycle Timing. SCL: Serial Clock, SDA: Serial Data I/O

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA

Note

:

The Write Cycle time twr is the time from a valid stop condition of a write sequence to the end of the internal

clear/write cycle.

Figure 6.

Data Validity

DATA

CHANGE

ALLOWED

DATA STABLE

DATA STABLE

SDA

SCL

Figure 7.

START and STOP Definitions

SDA

SCL

START

STOP