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EN56Q64-104HIP Datasheet(PDF) 29 Page - Eon Silicon Solution Inc.

Part # EN56Q64-104HIP
Description  64 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
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Manufacturer  EON [Eon Silicon Solution Inc.]
Direct Link  http://www.essi.com.tw
Logo EON - Eon Silicon Solution Inc.

EN56Q64-104HIP Datasheet(HTML) 29 Page - Eon Silicon Solution Inc.

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This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
or modifications due to changes in technical specifications.
29
EN25Q64
Rev. E, Issue Date: 2009/10/19
Quad Input / Output FAST_READ (EBh)
The Quad Input/Output FAST_READ (EBh) instruction is similar to the Dual I/O Fast Read (BBh)
instruction except that address and data bits are input and output through four pins. DQ0, DQ1, DQ2 and
DQ3 and four Dummy clocks are required prior to the data output. The Quad I/O dramatically reduces
instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.
The Quad Input/Output FAST_READ (EBh) instruction enable quad throughput of Serial Flash in read
mode. The address is latching on rising edge of CLK, and data of every four bits (interleave on 4 I/O
pins) shift out on the falling edge of CLK at a maximum frequency FR. The first address can be any
location. The address is automatically increased to the next higher address after each byte data is
shifted out, so the whole memory can be read out at a single Quad Input/Output FAST_READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing Quad Input/Output FAST_READ instruction, the following address/dummy/data out will perform
as 4-bit instead of previous 1-bit.
The sequence of issuing Quad Input/Output FAST_READ (EBh) instruction is: CS# goes low ->
sending Quad Input/Output FAST_READ (EBh) instruction -> 24-bit address interleave on DQ3, DQ2,
DQ1 and DQ0 -> 6 dummy cycles -> data out interleave on DQ3, DQ2, DQ1 and DQ0 -> to end Quad
Input/Output FAST_READ (EBh) operation can use CS# to high at any time during data out, as shown
in Figure 16.
The instruction sequence is shown in Figure 16.1 while using the Enable Quad I/O (EQIO) (38h) command.
Figure 16. Quad Input / Output Fast Read Instruction Sequence Diagram


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