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EN25S40 Datasheet(PDF) 8 Page - Eon Silicon Solution Inc.

Part No. EN25S40
Description  4 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector
Download  37 Pages
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Maker  EON [Eon Silicon Solution Inc.]
Homepage  http://www.essi.com.tw
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EN25S40 Datasheet(HTML) 8 Page - Eon Silicon Solution Inc.

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This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
or modifications due to changes in technical specifications.
8
EN25S40
Rev. A, Issue Date: 2009/04/28
In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
Table 3. Protected Area Sizes Sector Organization
Status Register
Content
Memory Content
BP2
Bit
BP1
Bit
BP0
Bit
Protect Sectors
Addresses
Density(KB)
0
0
0
None
None
None
0
0
1
0 to 111
000000h-06FFFFh
448KB
0
1
0
0 to 119
000000h-077FFFh
480KB
0
1
1
All
000000h-07FFFFh
512KB
1
0
0
None
None
None
1
0
1
0 to 123
000000h-07BFFFh
496KB
1
1
0
0 to 125
000000h-07DFFFh
504KB
1
1
1
All
000000h-07FFFFh
512KB
Hold Function
The Hold (HOLD#) signal is used to pause any serial communications with the device without resetting
the clocking sequence. However, taking this signal Low does not terminate any Write Status Register,
Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold
condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with Serial
Clock (CLK) being Low (as shown in Figure 4.).
The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides
with Serial Clock (CLK) being Low.
If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after
Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK)
being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.).
During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI)
and Serial Clock (CLK) are Don’t Care.
Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of the internal logic remains unchanged from the mo-
ment of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting
the internal logic of the device. To restart communication with the device, it is necessary to drive Hold
(HOLD#) High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to
the Hold condition.
Figure 4. Hold Condition Waveform


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