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EN25S40 Datasheet(PDF) 28 Page - Eon Silicon Solution Inc.

Part No. EN25S40
Description  4 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector
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Maker  EON [Eon Silicon Solution Inc.]
Homepage  http://www.essi.com.tw
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EN25S40 Datasheet(HTML) 28 Page - Eon Silicon Solution Inc.

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This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
or modifications due to changes in technical specifications.
28
EN25S40
Rev. A, Issue Date: 2009/04/28
Table 11. 75MHz AC Characteristics
(Ta = - 40°C to 85°C; VCC = 1.65-1.95V)
Symbol
Alt
Parameter
Min
Typ
Max
Unit
Serial Clock Frequency for:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, WRSR
D.C.
75
MHz
F
R
f
C
Serial Clock Frequency for:
Dual Fast Read 、Dual I/O
D.C.
50
MHz
f
R
Serial Clock Frequency for READ, RDSR, RDID
D.C.
33
MHz
t
CLH
1
Serial Clock High Time
6
ns
t
CLL
1
Serial Clock Low Time
6
ns
t
CLCH
2
Serial Clock Rise Time (Slew Rate)
0.1
V / ns
t
CHCL
2
Serial Clock Fall Time (Slew Rate)
0.1
V / ns
t
SLCH
t
CSS
CS# Active Setup Time
5
ns
t
CHSH
CS# Active Hold Time
5
ns
t
SHCH
CS# Not Active Setup Time
5
ns
t
CHSL
CS# Not Active Hold Time
5
ns
t
SHSL
t
CSH
CS# High Time
100
ns
t
SHQZ
2
t
DIS
Output Disable Time
6
ns
t
CLQX
t
HO
Output Hold Time
0
ns
t
DVCH
t
DSU
Data In Setup Time
2
ns
t
CHDX
t
DH
Data In Hold Time
5
ns
t
HLCH
HOLD# Low Setup Time ( relative to CLK )
5
ns
t
HHCH
HOLD# High Setup Time ( relative to CLK )
5
ns
t
CHHH
HOLD# Low Hold Time ( relative to CLK )
5
ns
t
CHHL
HOLD# High Hold Time ( relative to CLK )
5
ns
t
HLQZ
2
t
HZ
HOLD# Low to High-Z Output
6
ns
t
HHQX
2
t
LZ
HOLD# High to Low-Z Output
6
ns
t
CLQV
t
V
Output Valid from CLK ( 75 MHz )
8
ns
Output Valid from CLK ( 50 MHz )
9
ns
Output Valid from CLK ( 33 MHz )
13
ns
t
WHSL
3
Write Protect Setup Time before CS# Low
20
ns
t
SHWL
3
Write Protect Hold Time after CS# High
100
ns
t
DP
2
CS# High to Deep Power-down Mode
3
µs
t
RES1
2
CS# High to Standby Mode without Electronic
Signature read
3
µs
t
RES2
2
CS# High to Standby Mode with Electronic
Signature read
1.8
µs
t
W
Write Status Register Cycle Time
20
50
ms
t
PP
Page Programming Time
1.3
5
ms
t
SE
Sector Erase Time
0.09
0.3
s
t
BE
Block Erase Time
0.4
2
s
t
CE
Chip Erase Time
3.5
10
s
Note: 1.
t
CH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.


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