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ICS854S013BGLF Datasheet(PDF) 2 Page - Integrated Device Technology |
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ICS854S013BGLF Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 14 page ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY IDT™ / ICS™ LVDS FANOUT BUFFER 2 ICS854S013BG REV. A FEBRUARY 26, 2008 Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. Clock Input Function Table NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels. Number Name Type Description 1, 2 nQA0, QA0 Output Differential output pair. LVDS interface levels. 3, 8, 16 VDD Power Power supply pins. 4 PCLKA Input Pulldown Non-inverting differential clock input. 5 nPCLKA Input Pullup Inverting differential clock input. VDD/2 default when left floating. 6 PCLKB Input Pulldown Non-inverting differential clock input. 7 nPCLKB Input Pullup Inverting differential clock input. VDD/2 default when left floating. 9, 10 nQB0, QB0 Output Differential output pair. LVDS interface levels. 11 GND Power Power supply ground. 12, 13 nQB1, QB1 Output Differential output pair. LVDS interface levels. 14, 15 nQB2, QB2 Output Differential output pair. LVDS interface levels. 17, 18 nQA2, QA2 Output Differential output pair. LVDS interface levels. 19, 20 nQA1, QA1 Output Differential output pair. LVDS interface levels. Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k Ω RPULLDOWN Input Pulldown Resistor 51 k Ω Inputs Outputs Input to Output Mode Polarity PCLKA, PCLKB nPCLKA, nPCLKB QA[0:2], QB[0:2] nQA[0:2], nQB[0:2] 0 1 LOW HIGH Differential to Differential Non-Inverting 1 0 HIGH LOW Differential to Differential Non-Inverting 0 Biased; NOTE 1 LOW HIGH Single-ended to Differential Non-Inverting 1 Biased; NOTE 1 HIGH LOW Single-ended to Differential Non-Inverting Biased; NOTE 1 0 HIGH LOW Single-ended to Differential Inverting Biased; NOTE 1 1 LOW HIGH Single-ended to Differential Inverting |
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