Electronic Components Datasheet Search |
|
843SDNAGLF Datasheet(PDF) 7 Page - Integrated Device Technology |
|
843SDNAGLF Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 14 page ICS843SDN FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR 7 ICS843SDNAG REV. A FEBRUARY 19, 2009 LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 Ω applications, R1 and R2 can be 100 Ω. This can also be accomplished by removing R1 and making R2 50 Ω. Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination XTAL_IN XTAL_OUT Ro Rs Zo = Ro + Rs 50 Ω 0.1µf R1 R2 VCC VCC V CC - 2V 50 Ω 50 Ω RTT Z o = 50Ω Z o = 50Ω FOUT FIN RTT = Z o 1 ((V OH + VOL) / (VCC – 2)) – 2 3.3V 125 Ω 125 Ω 84 Ω 84 Ω Z o = 50Ω Z o = 50Ω FOUT FIN |
Similar Part No. - 843SDNAGLF |
|
Similar Description - 843SDNAGLF |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |