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CPC7232WTR Datasheet(PDF) 10 Page - Clare, Inc. |
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CPC7232WTR Datasheet(HTML) 10 Page - Clare, Inc. |
10 / 13 page CPC7232 10 www.clare.com R00E 2.1 Truth Table 2.2 Logic Timing Waveforms Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L ? H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when switch 7 is on. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON X X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X X H OFF OFF OFF OFF OFF OFF OFF OFF D N-1 D N D N+1 50% 50% 50% 50% D IN LE t WLE t SD 50% 50% CLK t SU t H t DO 50% D OUT t OFF t ON 90% 10% OFF ON CL 50% 50% t WCL V OUT (TYP) |
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