9LPRS535BGLF datasheet(5/17 Pages) IDT

Part #	9LPRS535BGLF

Description	48-pin CK505 for Intel Systems

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Manufacturer	IDT [Integrated Device Technology]

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5

Integrated

Circuit

Systems, Inc.

ICS9LPRS535

Datasheet

1461A—07/28/09

Absolute Maximum Ratings - DC Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Notes

Maximum Supply Voltage

VDDxxx

Supply Voltage

4.6

V

7

Maximum Supply Voltage

VDDxxx_IO

Low-Voltage Differential I/O Supply

3.8

V

7

Maximum Input Voltage

VIH

3.3V Inputs

4.6

V

4,5,7

Minimum Input Voltage

VIL

Any Input

GND - 0.5

V

4,7

Storage Temperature

Ts

-

-65

150

°C

4,7

Input ESD protection

ESD prot

Human Body Model

2000

V

6,7

1Guaranteed by design and characterization, not 100% tested in production.

2 Operation under these conditions is neither implied, nor guaranteed.

3 Maximum input voltage is not to exceed VDD

AC Electrical Characteristics - Low Power Differential Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS NOTES

Rising Edge Slew Rate

tSLR

Averaging on

2.5

4

V/ns

2, 3

Falling Edge Slew Rate

tFLR

Averaging on

2.5

4

V/ns

2, 3

Slew Rate Variation

tSLVAR

Averaging on

20

%

1, 10

Differential Voltage Swing

VSWING

Averaging off

300

mV

2

Crossing Point Voltage

VXABS

Averaging off

300

550

mV

1,4,5

Crossing Point Variation

VXABSVAR

Averaging off

140

mV

1,4,9

Maximum Output Voltage

VHIGH

Averaging off

1150

mV

1,7

Minimum Output Voltage

VLOW

Averaging off

-300

mV

1,8

Duty Cycle

DCYC

Averaging on

45

55

%

2

CPU[1:0] Skew

CPUSKEW10

Differential Measurement

100

ps

1

CPU[2_ITP:0] Skew

CPUSKEW20

Differential Measurement

150

ps

1

SRC[10:0] Skew

SRCSKEW

Differential Measurement

3000

ps

1,6,11

1Measurement taken for single ended waveform on a component test board (not in system)

2 Measurement taken from differential waveform on a component test board. (not in system)

3 Slew rate emastured through V_swing voltage range centered about differential zero

4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)

NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

5 Only applies to the differential rising edge (Clock rising, Clock# falling)

6 Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps.

7 The max voltage including overshoot.

8 The min voltage including undershoot.

9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross

10 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising

11 For PCIe Gen2 compliant devices, SRC 3, 4, 6, and 7 will have 0 ps nominal skew.

Electrical Characteristics - PCICLK/PCICLK_F

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS NOTES

Long Accuracy

ppm

see Tperiod min-max values

-100

100

ppm

1,2

33.33MHz output no spread

29.99700

30.00300

ns

2

33.33MHz output spread

30.08421

30.23459

ns

2

33.33MHz output no spread

29.49700

30.50300

ns

2

33.33MHz output nominal/spread

29.56617

30.58421

ns

2

Output High Voltage

VOH

IOH = -1 mA

2.4

V

1

Output Low Voltage

VOL

IOL = 1 mA

0.55

V

1

V OH @MIN = 1.0 V

-33

mA

1

VOH@MAX = 3.135 V

-33

mA

1

VOL @ MIN = 1.95 V

30

mA

1

VOL @ MAX = 0.4 V

38

mA

1

Rising Edge Slew Rate

tSLR

Measured from 0.8 to 2.0 V

1

4

V/ns

1

Falling Edge Slew Rate

tFLR

Measured from 2.0 to 0.8 V

1

4

V/ns

1

Pin to Pin Skew

tskew

VT = 1.5 V

250

ps

2

Intential PCI to PCI delay

tskew

VT = 1.5 V

100

200

ps

2

Duty Cycle

dt1

VT = 1.5 V

45

55

%

2

Jitter, Cycle to cycle

tjcyc-cyc

VT = 1.5 V

500

ps

2

Clock period

Tperiod

Absolute min/max period

Tabs

Output High Current

IOH

Output Low Current

IOL

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