FM28V020 - 32Kx8 FRAM

Rev. 1.1

Sept. 2009

Page 3 of 14

Functional Truth Table

/CE

/WE

A(14:3)

A(2:0)

Operation

H

X

X

X

Standby/Idle

↓

H

V

V

Read

L

H

No Change

Change

Page Mode Read

L

H

Change

V

Random Read

↓

L

V

V

/CE-Controlled Write

2

L

↓

V

V

/WE-Controlled Write

2, 3

L

↓

No Change

V

Page Mode Write

4

↑

X

X

X

Starts Precharge

Notes:

1)

H=Logic High, L=Logic Low, V=Valid Address, X=Don’t Care.

2)

For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.

3)

/WE-controlled write cycle begins as a Read cycle and A(14:3) is latched then.

4)

Addresses A(2:0) must remain stable for at least 15 ns during page mode operation.