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L9D340G64BG2 Datasheet(PDF) 65 Page - LOGIC Devices Incorporated |
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L9D340G64BG2 Datasheet(HTML) 65 Page - LOGIC Devices Incorporated |
65 / 155 page ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 TABLE 57: DERATING VALUE FOR tDS/tDH – AC150/DC100 - BASED DQ Slew Rate V/ns 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns DQS, DQS# Differential Slew Rate ∆tDS, ∆tDH Derating (ps) – AC150/DC100-Based Shaded cells indicate slew-rate combinations not supported LOGIC Devices Incorporated www.logicdevices.com May 19, 2009 LDS-L9D340G6BG2-A 65 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) PRELIMINARY INFORMATION L9D340G64BG2 High Performance, Integrated Memory Module Product 75 50 0 50 34 0 75 50 0 0 50 34 0 -4 75 50 0 0 0 50 34 0 -4 -10 58 8 8 8 8 42 8 4 -2 -8 16 16 16 16 15 16 12 6 0 -10 24 24 24 23 14 20 14 8 -2 -16 32 32 31 22 7 24 18 8 -6 -26 40 39 30 15 34 24 10 -10 Slew Rate (V/ns) tVAC at 175mV(ps) [MIN] tVAC at 150mV(ps) [MIN] >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 175 170 167 163 162 161 159 155 150 150 TABLE 58: REQUIRED TIME tVAC ABOVE VIH(AC) (BELOW VIL[AC]) FOR A VALID TRANSITION 75 57 50 38 34 29 22 13 0 0 |
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