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LAN9311-NZW Datasheet(PDF) 100 Page - SMSC Corporation |
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LAN9311-NZW Datasheet(HTML) 100 Page - SMSC Corporation |
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100 / 459 page  Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Revision 1.6 (08-18-09) 100 SMSC LAN9311/LAN9311i DATASHEET 8.3.1 16-Bit Bus Writes The host is required to perform two contiguous 16-bit writes to complete a single DWORD transfer. The DWORD must not cross a DWORD address boundary (A[2] and higher cannot change between a pair of writes). No ordering requirements exist. The host can access either the low or high word first, as long as the next write is performed on the other word. If a write to the same word is performed, the device disregards the transfer. Once both writes occur, an internal 32-bit write is performed to the appropriate register. 8.3.2 16-Bit Bus Read The host is required to perform two consecutive 16-bit reads to complete a single DWORD transfer. The DWORD must not cross a DWORD address boundary (A[2] and higher cannot change between a pair of writes). No ordering requirements exist. The host can access either the low or high word first, as long as the next read is performed from the other word. If a read to the same word is performed, the data read is invalid and should be re-read. However, this is not a fatal error. The LAN9311/LAN9311i will reset its read counters and restart a new cycle on the next read. Note: Some registers are readable as 16-bit registers. In this case, if desired, only one 16-bit read may be performed without the need to read the other word. If a register is 16-bit readable, it will be noted in its register description. 8.4 Host Endianess The LAN9311/LAN9311i supports big and little endian host byte ordering based upon the END_SEL pin. When END_SEL is low, host access is little endian. When END_SEL is high, host access is big endian. In a typical application, END_SEL is connected to a high-order address line, making endian selection address based. This highly flexible interface provides mixed endian access for registers and memory for both PIO and host DMA access. As an example, PIO transfers to/from the System CSRs can utilize a different byte ordering than host DMA transactions to/from the RX and TX Data FIFOs. All internal busses are 32-bit with little endian byte ordering. Logic within the host bus interface re- orders bytes based on the state of the endian select signal (END_SEL), and the state of the least significant address line (A1). Data path operations for the supported endian configurations are illustrated in Figure 8.1, "Little Endian Byte Ordering" and Figure 8.2, "Big Endian Byte Ordering". |
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