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LAN9303i-ABZJ Datasheet(PDF) 25 Page - SMSC Corporation |
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LAN9303i-ABZJ Datasheet(HTML) 25 Page - SMSC Corporation |
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25 / 366 page  Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII Datasheet SMSC LAN9303/LAN9303i 25 Revision 1.3 (08-27-09) DATASHEET Note 3.2 The pin names for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is enabled and a reverse connection is detected or manually selected, the RX and TX pins will be swapped internally. Note 3.3 Please refer to the LAN9303/LAN9303i Reference Schematic and LANCheck Schematic Checklist on the SMSC website for additional connection information. Table 3.3 LAN Port 1 & 2 Power and Common Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 Bias Reference EXRES AI Used for internal bias circuits. Connect to an external 12.4K ohm, 1% resistor to ground. 2 +3.3V Port 1 Analog Power Supply VDD33A1 P See Note 3.3. 2 +3.3V Port 2 Analog Power Supply VDD33A2 P See Note 3.3. 1 +3.3V Master Bias Power Supply VDD33BIAS P See Note 3.3. 1 Port 2 Transmitter +1.8V Power Supply VDD18TX2 P This pin is supplied from the internal PHY voltage regulator. This pin must be tied to the VDD18TX1 pin for proper operation. See Note 3.3. 1 Port 1 Transmitter +1.8V Power Supply VDD18TX1 P This pin must be connected directly to the VDD18TX2 pin for proper operation. See Note 3.3. Table 3.4 Port 0 MII/RMII Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 Port 0 MII Input Data 3 P0_IND3 IS (PD) MII MAC Mode: This pin is the receive data 3 bit from the external PHY to the switch. IS (PD) MII PHY Mode: This pin is the transmit data 3 bit from the external MAC to the switch. The pull-down and input buffer are disabled when the Isolate (VPHY_ISO) bit is set in the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). - RMII PHY Mode: This pin is not used. |
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Similar Description - LAN9303i-ABZJ |
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