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LAN9303i Datasheet(PDF) 29 Page - SMSC Corporation |
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LAN9303i Datasheet(HTML) 29 Page - SMSC Corporation |
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29 / 366 page  Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII Datasheet SMSC LAN9303/LAN9303i 29 Revision 1.3 (08-27-09) DATASHEET 1 Port 0 MII Output Data 0 P0_OUTD0 O8 MII MAC Mode: This pin is the transmit data 0 bit from the switch to the external PHY. O8 MII PHY Mode: This pin is the receive data 0 bit from the switch to the external MAC. The output driver is disabled when the Isolate (VPHY_ISO) bit is set in the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). O8 RMII PHY Mode: This pin is the receive data 0 bit from the switch to the external MAC. The output driver is disabled when the Isolate (VPHY_ISO) bit is set in the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). Port 0 Mode[0] Configuration Strap P0_MODE0 IS (PU) Note 3.5 This strap configures the mode for Port 0. See Note 3.4. The P0_MODE[2:0] configuration strap encoding is as follows: 000 = MII MAC mode 001 = MII PHY mode 010 = MII PHY mode 200 Mbps 12 ma clock output 011 = MII PHY mode 200 Mbps 16 ma clock output 100 = RMII PHY mode clock is 12 ma output 101 = RMII PHY mode clock is 16 ma output 110 = RMII PHY mode clock is input 111 = RESERVED 1 Port 0 MII Output Data Valid P0_OUTDV O8 MII MAC Mode: This pin is the TX_EN signal to the external PHY and indicates valid data on P0_OUTD[3:0]. O8 MII PHY Mode: This pin is the RX_DV signal to the external MAC. The output driver is disabled when the Isolate (VPHY_ISO) bit is set in the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). O8 RMII PHY Mode: This pin is the CRS_DV signal to the external MAC. The output driver is disabled when the Isolate (VPHY_ISO) bit is set in the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). Table 3.4 Port 0 MII/RMII Pins (continued) NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION |
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