SN75DP120

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SLLSE08 – OCTOBER 2009

ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply current under active operating

LP# = VCC, ML: VOD = 1200mVp-p,

165

200

mA

mode

2.7Gbps PRBS; AUX: VID = 1000mVp-p,

1Mbps PRBS; VDD= 3.6V, VCC=3.6V

Device power under power down

LP# = VCC, ML: VID = 0mVp-p,

8

12

mA

mode (D3) or standby main link

AUX: VID = 0mVp-p; VDD= 3.6V, VCC=3.6V

disabled

Low power current

LP# = 0V, VDD= 3.6V, VCC=3.6V HPD_INV,

1

10

µA

CAD_INV = NC, 0V

LP# = 0V, VDD= 3.6V, VCC=3.6V

400

640

HPD_INV=VCC

Supply current

VDD = 3.6V, HPD_INV = VDD

4

mA

D3 Powerdown or standby mode exit

Total time for the device to exit from D3 or standby

1.2

1.8

µs

time

state to active mode

HOT PLUG AND CABLE ADAPTER DETECT

The SN75DP120 has an integrated 125K

Ω pull down on the HPD_SINK input pin. The HPD and CAD timing

diagrams in this section are for the non-inverting case. The same timing diagrams apply for the inverting case

except the output is inverted. The VOH level of CAD_SRC follows that of VDD irrespective of CAD_INV setting.

However VOH for HPD_SRC depends on HPD_INV setting. When HPD_INV is low or left floating, HPD_SRC

VOH follows that of VDD. When HPD_INV = H then HPD_SRC VOH is set to 0.8V – 1.1V irrespective of VDD.

Explanation of HPD power management and interrupt behavior of the SN75DP120 is located in the Application

Information section at the end of the datasheet.

ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

HPD_INV, CAD_INV = L

High-level output voltage

3

V

(CAD_SRC and HPD_SRC)

CAD_SINK, HPD_SINK = H

High-level output voltage

2.25

V

(CAD_SRC and HPD_SRC)

CAD_SINK, HPD_SINK = H

High-level output voltage

1.62

1.8

V

(CAD_SRC and HPD_SRC)

CAD_SINK, HPD_SINK = H

High-level output voltage

0.1

V

(CAD_SRC and HPD_SRC)

CAD_SINK, HPD_SINK = L

Low-level output voltage

0.1

V

(CAD_SRC and HPD_SRC)

CAD_SINK, HPD_SINK = L

Low-level output voltage

0.1

V

(CAD_SRC and HPD_SRC)

CAD_SINK, HPD_SINK = L

HPD_INV = H

High-level output voltage

0.8

0.9

1.1

V

(HPD_SRC)

HPD_SINK = L

Low-level output voltage

0.1

V

(HPD_SRC)

HPD_SINK = H

High-level input current

–5

35

µA

(HPD_SINK, CAD_SINK, HPD_INV, CAD_INV)

(Leakage includes pull down resistor)

lLow-level input current

–5

35

µA

(HPD_SINK, CAD_SINK, HPD_INV, CAD_INV)

(Leakage includes pull down resistor)

Weak pull down resistor on HPD_SINK

100

125

150

k

Ω

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Product Folder Link(s): SN75DP120