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SN75DP120RHHR Datasheet(PDF) 9 Page - Texas Instruments |
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SN75DP120RHHR Datasheet(HTML) 9 Page - Texas Instruments |
9 / 27 page SN75DP120 www.ti.com SLLSE08 – OCTOBER 2009 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC Supply current under active operating LP# = VCC, ML: VOD = 1200mVp-p, 165 200 mA mode 2.7Gbps PRBS; AUX: VID = 1000mVp-p, 1Mbps PRBS; VDD= 3.6V, VCC=3.6V IPDWN Device power under power down LP# = VCC, ML: VID = 0mVp-p, 8 12 mA mode (D3) or standby main link AUX: VID = 0mVp-p; VDD= 3.6V, VCC=3.6V disabled Low power current LP# = 0V, VDD= 3.6V, VCC=3.6V HPD_INV, 1 10 µA CAD_INV = NC, 0V ILP LP# = 0V, VDD= 3.6V, VCC=3.6V 400 640 HPD_INV=VCC IDD Supply current VDD = 3.6V, HPD_INV = VDD 4 mA tPWDNEX D3 Powerdown or standby mode exit Total time for the device to exit from D3 or standby 1.2 1.8 µs time state to active mode HOT PLUG AND CABLE ADAPTER DETECT The SN75DP120 has an integrated 125K Ω pull down on the HPD_SINK input pin. The HPD and CAD timing diagrams in this section are for the non-inverting case. The same timing diagrams apply for the inverting case except the output is inverted. The VOH level of CAD_SRC follows that of VDD irrespective of CAD_INV setting. However VOH for HPD_SRC depends on HPD_INV setting. When HPD_INV is low or left floating, HPD_SRC VOH follows that of VDD. When HPD_INV = H then HPD_SRC VOH is set to 0.8V – 1.1V irrespective of VDD. Explanation of HPD power management and interrupt behavior of the SN75DP120 is located in the Application Information section at the end of the datasheet. ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HPD_INV, CAD_INV = L VOH3.3 High-level output voltage VDD = 3.3 V, IOH = –100 µA, 3 V (CAD_SRC and HPD_SRC) CAD_SINK, HPD_SINK = H VOH2.5 High-level output voltage VDD = 2.5 V, IOH = –100 µA, 2.25 V (CAD_SRC and HPD_SRC) CAD_SINK, HPD_SINK = H VOH1.8 High-level output voltage VDD = 1.8 V, IOH = –100 µA, 1.62 1.8 V (CAD_SRC and HPD_SRC) CAD_SINK, HPD_SINK = H VOL3.3 High-level output voltage VDD = 3.3 V, IOL = 100 µA, 0.1 V (CAD_SRC and HPD_SRC) CAD_SINK, HPD_SINK = L VOL2.5 Low-level output voltage VDD = 2.5 V, IOL = 100 µA, 0.1 V (CAD_SRC and HPD_SRC) CAD_SINK, HPD_SINK = L VOL1.8 Low-level output voltage VDD = 1.8 V, IOL = 100 µA, 0.1 V (CAD_SRC and HPD_SRC) CAD_SINK, HPD_SINK = L HPD_INV = H VOH1.1 High-level output voltage IOH = –100 µA, 0.8 0.9 1.1 V (HPD_SRC) HPD_SINK = L VOL1.1 Low-level output voltage IOH = 100 µA, 0.1 V (HPD_SRC) HPD_SINK = H IIH High-level input current VIH = 2.0 V, VDD = 3.6 V –5 35 µA (HPD_SINK, CAD_SINK, HPD_INV, CAD_INV) (Leakage includes pull down resistor) IL lLow-level input current VIL = 0.8 V, VDD = 3.6 V –5 35 µA (HPD_SINK, CAD_SINK, HPD_INV, CAD_INV) (Leakage includes pull down resistor) RHPDIN Weak pull down resistor on HPD_SINK 100 125 150 k Ω Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): SN75DP120 |
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