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MAX17021GTL+ Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX17021GTL+ Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 48 page Dual-Phase, Quick-PWM Controllers for IMVP-6+/IMVP-6.5 CPU Core Power Supplies 4 _______________________________________________________________________________________ ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGDIN = VPSI = VILIM = 5V, V3P3 = 3.3V, DPRSLPVR = GNDS = GND, VCSP1 = VCSN1 = VCSP2 = VCSN1 = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN1, D6–D0 = [0101000]; MAX17082/MAX17482: VSLOW = 5V; MAX17021: DPRSTP = GND; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Quiescent Supply Current (V3P3) I3P3 Measured at V3P3, FB forced within the CLKEN power-good window 2 4 μA Shutdown Supply Current (VCC) ICC,SDN Measured at VCC, SHDN = GND, TA = +25°C 0.01 1 μA Shutdown Supply Current (VDD) IDD,SDN Measured at VDD, SHDN = GND, TA = +25°C 0.01 1 μA Shutdown Supply Current (V3P3) I3P3,SDN Measured at V3P3, SHDN = GND, TA = +25°C 0.01 1 μA FAULT PROTECTION Skip mode after output reaches the regulation voltage or PWM mode; measured at FB with respect to the voltage target set by the VID code; see Table 4. 250 300 350 mV IMVP-6.5 (MAX17082) 1.45 1.50 1.55 Soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage; measured at FB IMVP-6+ (MAX17021) 1.75 1.80 1.85 Output Overvoltage- Protection Threshold (MAX17021/MAX17082 Only) VOVP Minimum OVP threshold; measured at FB 0.8 V Output Overvoltage- Propagation Delay (MAX17021/MAX17082 Only) tOVP FB forced 25mV above trip threshold 10 μs Output Undervoltage- Protection Threshold VUVP Measured at FB with respect to the voltage target set by the VID code; see Table 4 -450 -400 -350 mV Output Undervoltage- Propagation Delay tUVP FB forced 25mV below trip threshold 10 μs CLKEN Startup Delay and Boot Time Period tBOOT Measured from the time when FB reaches the boot target voltage (Note 2) 20 60 100 μs PWRGD Startup Delay Measured at startup from the time when CLKEN goes low 3 6.5 10 ms Lower threshold, falling edge (undervoltage) -350 -300 -250 CLKEN and PWRGD Threshold Measured at FB with respect to the voltage target set by the VID code; see Table 4, 20mV hysteresis (typ) Upper threshold, rising edge (overvoltage) +150 +200 +250 mV CLKEN and PWRGD Delay FB forced 25mV outside the PWRGD trip thresholds 10 μs PHASEGD Delay V(CCI,FB) forced 25mV outside trip thresholds 10 μs |
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