4

Integrated Silicon Solution, Inc.

Rev. 00A

03/31/08

72 Mb (2M x 36 & 4M x 18)

DDR-IIP (Burst of 2) CIO Synchronous SRAMs

Block Diagram

2M x 36

(4M x 18)

Memory

Array

Write Driver

Select Output Control

Data

Reg

Add Reg &

Control

Logic

Clock

Gen

36

(or 18)

72

(or 36)

36 (or 18)

DQ (Data-Out

CQ, CQ

(Echo Clock Out)

Address

LD

R/W

K

K

4 (or 2)

20 (or 21)

20 (or 21)

36 (or 18)

& Data-In)

A0

Burst

Control

36 (or 18)

SRAM Features

Read Operations

The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R/W in

active high state at the rising edge of the K clock. The K and K clocks are also used to control the timing to

the outputs. The data corresponding to the first address is clocked 2.5 cycles later by the rising edge of the

K clock. The data corresponding to the second burst is clocked 3 cycles later by the following rising edge of

the K clock. A set of free-running echo clocks, CQ and CQ, are produced internally with timings identical to

the data-outs. The echo clocks can be used as data capture clocks by the receiver device.

Whenever LD is low, a new address is registered at the rising edge of the K clock. A NOP operation (LD is

high) does not terminate the previous read. The output drivers disable automatically to a high state.

Write Operations

Write operations can also be initiated at every rising edge of the K clock whenever R/W is low. The write

address is also registered at that time. When the address needs to change, LD needs to be low

simultaneously to be registered by the rising edge of K. Again, the write always occurs in bursts of two.

Because of its common I/O architecture, the data bus must be tri-stated at least one cycle before the new

data-in is presented at the DQ bus.

The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the

burst, is presented one cycle later or at the rising edge of the next K clock. The data-in corresponding to the

second write burst address follows next, registered by the rising edge of K.