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SC9S12XS64J1M Datasheet(PDF) 74 Page - Freescale Semiconductor, Inc |
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SC9S12XS64J1M Datasheet(HTML) 74 Page - Freescale Semiconductor, Inc |
74 / 736 page Port Integration Module (S12XSPIMV1) S12XS Family Reference Manual, Rev. 1.09 74 Freescale Semiconductor 2.3.5 Port A Data Direction Register (DDRA) 2.3.6 Port B Data Direction Register (DDRB) Address 0x0002 (PRR) Access: User read/write1 1 Read: Anytime. The data source depends on the data direction value. Write: Anytime. 76543210 R DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 W Reset 00000000 Figure 2-3. Port A Data Direction Register (DDRA) Table 2-6. DDRA Register Field Descriptions Field Description 7-0 DDRA Port A Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input Address 0x0003 (PRR) Access: User read/write1 1 Read: Anytime. The data source depends on the data direction value. Write: Anytime. 76543210 R DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 W Reset 00000000 Figure 2-4. Port B Data Direction Register (DDRB) Table 2-7. DDRB Register Field Descriptions Field Description 7-0 DDRB Port B Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input |
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