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SC9S12XS64J1M Datasheet(PDF) 56 Page - Freescale Semiconductor, Inc |
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SC9S12XS64J1M Datasheet(HTML) 56 Page - Freescale Semiconductor, Inc |
56 / 736 page Device Overview S12XS Family S12XS Family Reference Manual, Rev. 1.09 56 Freescale Semiconductor 1.9 Oscillator Configuration The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check is ongoing. This is the case for: • Power on reset or low-voltage reset • Clock monitor reset • Any reset while in self-clock mode or full stop mode The selected oscillator configuration is frozen with the rising edge of the RESET pin in any of these above described reset cases. Figure 1-7. Loop Controlled Pierce Oscillator Connections (XCLKS = 1) Figure 1-8. Full Swing Pierce Oscillator Connections (XCLKS = 0) Figure 1-9. External Clock Connections (XCLKS = 0) MCU EXTAL XTAL VSSPLL Crystal or Ceramic Resonator C2 C1 MCU EXTAL XTAL RS RB VSSPLL Crystal or Ceramic Resonator C2 C1 RB=1MΩ ; RS specified by crystal vendor MCU EXTAL XTAL CMOS-Compatible External Oscillator Not Connected |
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Similar Description - SC9S12XS64J1M |
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