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SC9S12XS256J1C Datasheet(PDF) 83 Page - Freescale Semiconductor, Inc |
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SC9S12XS256J1C Datasheet(HTML) 83 Page - Freescale Semiconductor, Inc |
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83 / 736 page  Port Integration Module (S12XSPIMV1) S12XS Family Reference Manual, Rev. 1.09 Freescale Semiconductor 83 2.3.18 Port T Data Register (PTT) Table 2-15. DDRK Register Field Descriptions Field Description 7,5-0 DDRK Port K Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input Address 0x0240 Access: User read/write1 1 Read: Anytime. The data source depends on the data direction value. Write: Anytime. 76543210 R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W Altern. Function IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 (PWM7) (PWM6) (PWM5) (PWM4) ———— — — VREG_API ————— Reset 00000000 Figure 2-16. Port T Data Register (PTT) Table 2-16. PTT Register Field Descriptions Field Description 7-6, 4 PTT Port T general purpose input/output data—Data Register, TIM output, routed PWM output When not used with the alternative function, the associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. • The TIM output function takes precedence over the routed PWM and the general purpose I/O function if the related channel is enabled. • The routed PWM function takes precedence over the general purpose I/O function if the related channel is enabled. |
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