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SC9S12XS64J1CR Datasheet(PDF) 20 Page - Freescale Semiconductor, Inc |
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SC9S12XS64J1CR Datasheet(HTML) 20 Page - Freescale Semiconductor, Inc |
20 / 736 page Device Overview S12XS Family S12XS Family Reference Manual, Rev. 1.09 20 Freescale Semiconductor • INT (interrupt module) — Seven levels of nested interrupts — Flexible assignment of interrupt sources to each interrupt level. — External non-maskable high priority interrupt (XIRQ) — The following inputs can act as Wake-up Interrupts – IRQ and non-maskable XIRQ – CAN receive pins – SCI receive pins – Depending on the package option up to 20 pins on ports J, H and P configurable as rising or falling edge sensitive • MMC (module mapping control) • DBG (debug module) — Monitoring of CPU bus with tag-type or force-type breakpoint requests — 64 x 64-bit circular trace buffer captures change-of-flow or memory access information • BDM (background debug mode) • OSC_LCP (oscillator) — Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal — Good noise immunity — Full-swing Pierce option utilizing a 2MHz to 40MHz crystal — Transconductance sized for optimum start-up margin for typical crystals • IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation) — No external components required — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) • CRG (clock and reset generation) — COP watchdog — Real time interrupt — Clock monitor — Fast wake up from STOP in self clock mode • Memory Options — 64K, 128K and 256K byte Flash — Flash General Features – 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure correction and double fault detection – Erase sector size 1024 bytes – Automated program and erase algorithm – Protection scheme to prevent accidental program or erase – Security option to prevent unauthorized access – Sense-amp margin level setting for reads — 4K and 8K byte Data Flash space |
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