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IS42S16100E-5TL Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS42S16100E-5TL Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
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1 / 82 page  Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. D 08/24/09 Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. IS42S16100E IS45S16100E SEPTEMBER 2009 FEATURES • Clock frequency: 200, 166, 143 MHz • Fullysynchronous;allsignalsreferencedtoa positive clock edge • Twobankscanbeoperatedsimultaneouslyand independently • DualinternalbankcontrolledbyA11(bankselect) • Single3.3Vpowersupply • LVTTLinterface • Programmableburstlength –(1,2,4,8,fullpage) • Programmableburstsequence: Sequential/Interleave • 2048refreshcyclesevery32ms(Com,Ind,A1 grade)or16ms(A2grade) • Randomcolumnaddresseveryclockcycle • ProgrammableCASlatency(2,3clocks) • Burstread/writeandburstread/singlewrite operations capability • Burstterminationbyburststopand precharge command • BytecontrolledbyLDQMandUDQM • Packages:400-mil50-pinTSOP-IIand60-ball TF-BGA • TemperatureGrades: Commercial(0oC to +70oC) Industrial(-40oCto+85oC) AutomotiveA1(-40oCto+85oC) AutomotiveA2(-40oCto+105oC) DESCRIPTION ISSI’s16MbSynchronousDRAMIS42/4516100Eis organizedasa524,288-wordx16-bitx2-bankfor improvedperformance.ThesynchronousDRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM PIN CONFIGURATIONS 50-Pin TSOP (Type II) PIN DESCRIPTIONS A0-A10 RowAddressInput A11 BankSelectAddress A0-A7 Column Address Input DQ0toDQ15 DataDQ CLK SystemClockInput CKE ClockEnable CS Chip Select RAS RowAddress Strobe Command CAS Column Address Strobe Command WE WriteEnable LDQM LowerBye,Input/OutputMask UDQM UpperBye,Input/OutputMask VDD Power GND Ground VDDQ PowerSupplyforDQPin GNDQ GroundforDQPin NC NoConnection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VDD DQ0 DQ1 GNDQ DQ2 DQ3 VDDQ DQ4 DQ5 GNDQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VDD GND DQ15 DQ14 GNDQ DQ13 DQ12 VDDQ DQ11 DQ10 GNDQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 GND |
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