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MC10XS3412DPNA Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc

Part No. MC10XS3412DPNA
Description  Quad High Side Switch (Dual 10 mOhm, Dual 12 mOhm)
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Maker  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
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MC10XS3412DPNA Datasheet(HTML) 24 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
24
Freescale Semiconductor
10XS3412
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 10XS3412 is one in a family of devices designed for
low-voltage automotive lighting applications. Its four low
RDS(ON) MOSFETs (dual 10 mΩ, dual 12 mΩ) can control
four separate 55 W / 28 W bulbs and/or Xenon modules.
Programming, control and diagnostics are accomplished
using a 16-bit SPI interface. Its output with selectable slew-
rate improves electromagnetic compatibility (EMC) behavior.
Additionally, each output has its own parallel input or SPI
control for pulse-width modulation (PWM) control if desired.
The 10XS3412 allows the user to program via the SPI the
fault current trip levels and duration of acceptable lamp
inrush. The device has fail-safe mode to provide fail-safe
functionality of the outputs in case of MCU damaged.
FUNCTIONAL PIN DESCRIPTION
OUTPUT CURRENT MONITORING (CSNS)
The Current Sense pin provides a current proportional to
the designated HS0:HS3 output or a voltage proportional to
the temperature on the GND flag. That current is fed into a
ground-referenced resistor (4.7 k
Ω typical) and its voltage is
monitored by an MCU's A/D. The output type is selected via
the SPI. This pin can be tri-stated through SPI.
DIRECT INPUTS (IN0, IN1, IN2, IN3)
Each IN input wakes the device. The IN0:IN3 high side
input pins are also used to directly control HS0:HS3 high side
output pins. In case of the outputs are controlled by PWM
module, the external PWM clock is applied to IN0 pin. These
pins are to be driven with CMOS levels, and they have a
passive internal pull-down, RDWN.
FAULT STATUS (FS)
This pin is an open drain configured output requiring an
external pull-up resistor to VDD for fault reporting. If a device
fault condition is detected, this pin is active LOW. Specific
device diagnostics and faults are reported via the SPI SO pin.
WAKE
The wake input wakes the device. An internal clamp
protects this pin from high damaging voltages with a series
resistor (10 k
Ω typ). This input has a passive internal pull-
down, RDWN.
RESET (RST)
The reset input wakes the device. This is used to initialize
the device configuration and fault registers, as well as place
the device in a low-current Sleep Mode. The pin also starts
the watchdog timer when transitioning from logic [0] to
logic [1]. This pin has a passive internal pull-down, RDWN.
CHIP SELECT (CS)
The CS pin enables communication with the master
microcontroller (MCU). When this pin is in a logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 10XS3412 latches
in data from the Input Shift registers to the addressed
registers on the rising edge of CS. The device transfers status
information from the power output to the Shift register on the
falling edge of CS. The SO output driver is enabled when CS
is logic [0]. CS should transition from a logic [1] to a logic [0]
state only when SCLK is a logic [0]. CS has an active internal
pull-up from VDD, IUP.
SERIAL CLOCK (SCLK)
The SCLK pin clocks the internal shift registers of the
10XS3412 device. The serial input (SI) pin accepts data into
the input shift register on the falling edge of the SCLK signal
while the serial output (SO) pin shifts data information out of
the SO line driver on the rising edge of the SCLK signal. It is
important the SCLK pin be in a logic low state whenever CS
makes any transition. For this reason, it is recommended the
SCLK pin be in a logic [0] whenever the device is not
accessed (CS logic [1] state). SCLK has an active internal
pull-down. When CS is logic [1], signals at the SCLK and SI
pins are ignored and SO is tri-stated (high-impedance) (see
Figure 9, page 27). SCLK input has an active internal pull-
down, IDWN.
SERIAL INPUT (SI)
This is a serial interface (SI) command data input pin.
Each SI bit is read on the falling edge of SCLK. A 16-bit
stream of serial data is required on the SI pin, starting with
D15 (MSB) to D0 (LSB). The internal registers of the
10XS3412 are configured and controlled using a 5-bit
addressing scheme described in Table 10, page 35. Register
addressing and configuration are described in Table 11,
page 36. SI input has an active internal pull-down, IDWN.
DIGITAL DRAIN VOLTAGE (VDD)
This pin is an external voltage input pin used to supply
power to the SPI circuit. In the event VDD is lost (VDD Failure),
the device goes to Fail-safe Mode.


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