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ADP1043A Datasheet(PDF) 29 Page - Analog Devices |
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ADP1043A Datasheet(HTML) 29 Page - Analog Devices |
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29 / 72 page  ADP1043A Rev. 0 | Page 29 of 72 COMMUNICATION I2C INTERFACE Control of the ADP1043A is carried out via the I2C interface. The ADP1043A is connected to the I2C bus as a slave device under the control of a master device. I2C Address The I2C address of the ADP1043A is set by connecting an external resistor from the ADD pin to AGND. Table 5 lists the recommended resistor values and the associated I2C addresses. Eight different addresses can be used. If an incorrect resistor value is used and the resulting I2C address is close to a threshold between two addresses, a flag is set (address flag in Register 0x03, Bit 5; see Table 11). The recommended values in Table 5 can vary by ±2 kΩ; the ADP1043A still reports the same address. Therefore, it is recom- mended that 1% tolerance resistors be used on the ADD pin. I2C Address 0x58 is the broadcast address, which allows multiple parts to be written to simultaneously. By using the broadcast address instead of a specific I2C address from Table 5, all ADP1043A devices on the I2C bus are written to. The broadcast address can be used for write commands only. Table 5. Recommended Resistor Values for I2C Addresses I2C Address Resistor Value (kΩ) 0x50 9 (or connect the ADD pin directly to AGND) 0x51 27 0x52 45 0x53 63 0x54 81 0x55 98 0x56 116 0x57 134 (or connect the ADD pin directly to VDD) General I2C Timing The ADP1043A has a timeout feature to protect against a fault condition on the SDA line. The I2C interface monitors the SDA line and, if it stays low for time 0.65 ms < t_low < 1.3 ms, the I2C interface is reset and waits for another start condition. The I2C specification defines specific conditions for different types of read and write operations. General I2C read and write operations are shown in the timing diagrams of Figure 32, Figure 33, and Figure 34, and are described in this section. The general I2C protocol operates as follows: 1. The master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, SDA, while the serial clock line, SCL, remains high. This indicates that a data stream follows. All slave peri- pherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit slave address (MSB first) plus a R/W bit, which determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). 2. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. 3. Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to- high transition when the clock is high may be interpreted as a stop signal. 4. If the operation is a write operation, the first data byte after the slave address is a command byte that tells the slave device what to expect next. It may be an instruction, such as telling the slave device to expect a block write, or it may be a register address that tells the slave where subsequent data is to be written. 5. Because data can flow in only one direction, as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before a read operation, it may be necessary to first perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. 6. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as a no acknowledge bit. The master takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. If several read or write operations must be performed in succes- sion, the master can send a repeat start condition instead of a stop condition to begin a new operation. |
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