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ADN2531ACPZ-WP Datasheet(PDF) 16 Page - Analog Devices

Part No. ADN2531ACPZ-WP
Description  11.3 Gbps, Active Back-Termination, Differential Laser Diode Driver
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADN2531ACPZ-WP Datasheet(HTML) 16 Page - Analog Devices

 
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ADN2531
Rev. 0 | Page 16 of 20
perates,
CB layout to obtain
n
en
se multiple capacitors in
FP+ and XFP modules, contact sales. For guidelines on the
rface-mount assembly of the ADN2531, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP)
, on www.analog.com.
DESIGN EXAMPLE
Assuming that the impedance of the TOSA is 12 Ω, the forward
voltage of the laser at low current is VF = 1.5 V, IBIAS = 40 mA,
IMOD = 40 mA, and VCC = 3.3 V, this design example calculates
The headroom for the IBIAS, IMODP, and IMODN pins.
The typical voltage required at the BSET and MSET pins to
produce the desired bias and modulation currents.
The IBIAS monitor accuracy over the IBIAS current range.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Table 1.
Considering the typical application circuit shown in Figure 40,
the voltage at the IBIAS pin can be written as
VIBIAS
= VCC − VF − (IBIAS × RTOSA) − VLA
e:
CC
is the supply voltage.
VF
is the forward voltage across the laser at low current.
RTOSA
is the resistance of the TOSA.
VLA
is the dc voltage drop across L5, L6, L7, and L8.
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.6 V, as specified by the minimum
IBIAS compliance specification in Table 1.
Assuming that the voltage drop across the 50 Ω transmission lines
is negligible and that VLA = 0 V, VF = 1.5 V, and IBIAS = 40 mA,
VIBIAS
= 3.3 − 1.5 − (0.04 × 12) = 1.32 V
Therefore, VIBIAS = 1.32 V > 0.6 V, which satisfies the requirement
COMPLIANCE_MAX
CC
atisfies the
ulate the h
a
urrent pins
IMO
he
CC
e to the ac-co
led
0 Ω becau
is
roper
operation of the ADN2531, t
pin should
in
region shown
in Figure 36.
ing the dc
ltage dro
mA,
nim
odulation
qual
VCC
− (IMOD × 12)/2 = VCC − 0.24 V
Therefore, VCC − 0.24 > VCC − 1.1 V, which satisfies the
requirement.
The maximum voltage at the modulation output pins is equal to
VCC
+ (IMOD × 12)/2 = VCC + 0.24 V
Therefore, VCC + 0.24 < VCC + 1.1 V, which satisfies the
requirement.
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to ensure
proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculations
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2531 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET voltage to
IBIAS gain specified in Table 1. Assuming that IBIAS = 40 mA and that
IBIAS/VBSET = 100 mA/V (which is the typical IBIAS/VBSET ratio), the
BSET voltage is given by
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2531 o
care should be taken when designing the P
optimum performance. For example, use controlled impedance
transmission lines for high speed signal paths, and keep the
length of transmission lines as short as possible to reduce losses
and pattern-dependent jitter. In addition, the PCB layout must
be symmetrical, both on the DATAP and DATAN inputs and o
the IMODP and IMODN outputs, to ensure a balance between
the differential signals.
Furthermore, all VCC and GND pins must be connected to
solid copper planes by using low inductance connections. Wh
these connections are made through vias, multiple vias can be
connected in parallel to reduce the parasitic inductance. Each
GND pin must be locally decoupled to VCC with high quality
capacitors (see Figure 40). If proper decoupling cannot be
achieved using a single capacitor, u
parallel for each GND pin. A 20 μF tantalum capacitor must be
used as the general decoupling capacitor for the entire module.
For recommended PCB layouts, including those suitable for the
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
VCOMPLIANCE_MAX
= VCC − 0.75 − 4.4 × IBIAS (A)
For this example,
V
= V
− 0.75 − 4.4 × 0.04 = 2.374 V
S
su
wher
V
Therefore, VIBIAS = 1.32 V < 2.374 V, which s
requirement.
To calc
eadroom t the modulation c
(IMODP and
to V
du
DN), t
up
voltage has a dc component equal
configuration and a swing equal to
IMOD × 5
se RTOSA
less than 100 Ω. For p
he voltage at each modulation
output
be with
the normal operation
Assum
vo
p across L1, L2, L3, and L4 is 0 V
and IMOD is 40
output pins is e
the mi
to
um voltage at the m
V
4
.
0
100
40
mA/V
100
BSET
V
(mA)
=
=
= BIAS
I
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in Table 1.
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
K
I
V
MOD
MSET =
where K is the MSET voltage to IMOD ratio.


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