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SC9S12HY64J0MLL Datasheet(PDF) 72 Page - Freescale Semiconductor, Inc |
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SC9S12HY64J0MLL Datasheet(HTML) 72 Page - Freescale Semiconductor, Inc |
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72 / 790 page  Port Integration Module (S12HYPIMV1) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 72 Freescale Semiconductor 2.3.4 Port B Data Register (PORTB) 2.3.5 Port A Data Direction Register (DDRA) Address 0x0001 (PRR) Access: User read/write1 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB7 W Altern. Function BP3 BP2 BP1 BP0 FP39 FP38 FP37 FP28 Reset 00000000 Figure 2-2. Port B Data Register (PORTB) Table 2-5. PORTB Register Field Descriptions Field Description 7-0 PB Port B general purpose input/output data—Data Register, LCD segment driver output The associated pin can be used as general purpose I/O when not used as alternative function. In general purpose output mode the register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. • The LCD segment driver output takes precedence over the general purpose I/O function if the related LCD segment is enabled. Address 0x0002 (PRR) Access: User read/write1 1 Read: Anytime Write: Anytime 76543210 R DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 W Reset 00000000 Figure 2-3. Port A Data Direction Register (DDRA) |
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