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SC9S12HY64J0VLH Datasheet(PDF) 55 Page - Freescale Semiconductor, Inc |
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SC9S12HY64J0VLH Datasheet(HTML) 55 Page - Freescale Semiconductor, Inc |
55 / 790 page Port Integration Module (S12HYPIMV1) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 55 Table 2-1 shows all the pins and their functions that are controlled by the Port Integration Module. NOTE If there is more than one function associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority). Table 2-1. Pin Functions and Priorities Port Pin Name Pin Function & Priority1 I/O Description Pin Function after Reset - BKGD MODC 2 I MODC input during RESET BKGD BKGD I/O BDM communication pin AD PAD[7:0] AN[7:0] I ATD analog GPIO KWAD[7:0] I Key Wakeup GPIO I/O General purpose A PA[7:4] FP[36:33] O LCD frontplane segment driver output GPIO GPIO I/O General purpose PA[3] FP[32] O LCD frontplane segment driver output API_EXTCLK O API output GPIO I/O General purpose PA[2] FP[31] O LCD frontplane segment driver output GPIO I/O General purpose PA[1] FP[30] O LCD frontplane segment driver output XIRQ I Non-maskable level-sensitive interrupt GPIO I/O General purpose PA[0] FP[29] O LCD frontplane segment driver output IRQ I Maskable level or falling edge-sensitive interrupt GPIO I/O General purpose B PB[7:4] BP[3:0] O LCD backplane segment driver output GPIO GPIO I/O General purpose PB[3:0] FP[39:37,28] O LCD frontplane segment driver output GPIO I/O General purpose |
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