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SC9S12HY64J0VLH Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc |
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SC9S12HY64J0VLH Datasheet(HTML) 49 Page - Freescale Semiconductor, Inc |
49 / 790 page Device Overview MC9S12HY/HA-Family MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 49 1.11.3 Effects of Reset When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections for register reset states. On each reset, the Flash module executes a reset sequence to load Flash configuration registers. 1.11.3.1 Flash Configuration Reset Sequence Phase On each reset, the Flash module will hold CPU activity while loading Flash module registers from the Flash memory. If double faults are detected in the reset phase, Flash module protection and security may be active on leaving reset. This is explained in more detail in the Flash module section. 1.11.3.2 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. 1.11.3.3 I/O Pins Refer to the PIM section for reset configurations of all peripheral module ports. Vector base+ 0x9E TIM1 timer overflow I bit TIM1TSRC2 (TOI) Vector base+ 0x9C TIM1 Pulse accumulator A overflow I bit TIM1PACTL (PAOVI) Vector base + 0x9A TIM1 Pulse accumulator input edge I bit TIM1PACTL (PAI) Vector base+ 0x98 Reserved Vector base + 0x96 Motor Control Timer Overflow I-Bit MCCTL1 (MCOCIE) Vector base + 0x94 to Vector base + 0x90 Reserved Vector base + 0x8E Port T I bit PIET (PIET7-PIET0) Vector base+ 0x8C PWM emergency shutdown I bit PWMSDN (PWMIE) Vector base + 0x8A Low-voltage interrupt (LVI) I bit CPMUCTRL (LVIE) Vector base + 0x88 Autonomous periodical interrupt (API) I bit CPMUAPICTRL (APIE) Vector base + 0x86 High Temperature Interrupt I bit CPMUHTCL (HTIE) Vector base + 0x84 ATD Compare Interrupt I bit ATDCTL2 (ACMPIE) Vector base + 0x82 Reserved Vector base + 0x80 Spurious interrupt — None 1. 16 bits vector address based Table 1-12. Interrupt Vector Locations (Sheet 3 of 3) Vector Address(1) Interrupt Source CCR Mask Local Enable |
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