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SC9S12HY64J0CLH Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc |
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SC9S12HY64J0CLH Datasheet(HTML) 13 Page - Freescale Semiconductor, Inc |
13 / 790 page Device Overview MC9S12HY/HA-Family MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 13 1.2.2 Chip-Level Features On-chip modules available within the family include the following features: • S12 CPU core • Maximum 64MHZ core freqency, 32MHZ bus frequency • Up to 64 Kbyte on-chip flash with ECC • 4 Kbyte data flash with ECC • Up to 4 Kbyte on-chip SRAM • Phase locked loop (IPLL) frequency multiplier with internal filter • 4–16 MHz amplitude controlled Pierce oscillator • 1 MHz internal RC oscillator • Two timer modules (TIM0 and TIM1) supporting input/output channels that provide a range of 16- bit input capture, output compare, counter and pulse accumulator functions • Pulse width modulation (PWM) module with up to 8 x 8-bit channels • Up to 8-channel, 10-bit resolution successive approximation analog-to-digital converter (ATD) • Up to 40x4 LCD driver • PWM motor controller (MC) with up to 16 high current drivers • Output slew rate control on Motor driver pad • One serial peripheral interface (SPI) module • One Inter-IC bus interface (IIC) module • One serial communication interface (SCI) module supporting LIN communications • One multi-scalable controller area network (MSCAN) module (supporting CAN protocol 2.0A/B) • On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages • Autonomous periodic interrupt (API) • Up to 22 key wakeup inputs 1.3 Module Features The following sections provide more details of the modules implemented on the MC9S12HY/HA family. 1.3.1 S12 16-Bit Central Processor Unit (CPU) The S12 CPU is a high-speed, 16-bit processing unit that has a programming model identical to that of the industry standard M68HC11 central processor unit (CPU). • Full 16-bit data paths support efficient arithmetic operation and high-speed math execution • Supports instructions with odd byte counts, including many single-byte instructions. This allows much more efficient use of ROM space. • Extensive set of indexed addressing capabilities, including: — Using the stack pointer as an indexing register in all indexed operations — Using the program counter as an indexing register in all but auto increment/decrement mode |
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