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ADAU1381BCPZ-RL Datasheet(PDF) 45 Page - Analog Devices |
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ADAU1381BCPZ-RL Datasheet(HTML) 45 Page - Analog Devices |
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45 / 84 page  ADAU1381 Rev. 0| Page 45 of 84 Register 16385 (0x4001), Regulator Control Bits[2:1], Regulator Output Level These bits set the regulated voltage output for the digital core, DVDDOUT. After the initialization sequence has completed, the regulator output is set to 1.4 V. The recommended regulator output level when the device begins to process audio is 1.5 V. Therefore, this register should be set to 1.5 V when the sound engine is being configured. Register 16386 (0x4002), PLL Control This is a 48-bit register that must be written to in a single burst write. PLL operating parameters are used to scale the MCLK input to the desired clock core in order to obtain an appropriate PLL clock (PLL output frequency). The PLL can be configured for either fractional or integer-N type MCLK inputs. Bits[47:40], Denominator MSB Byte 1, M[15:8] of the denominator (M) for fractional part of feed- back divider. This is concatenated with Denominator LSB, M[7:0]. Bits[39:32], Denominator LSB Byte 0, M[7:0] of the denominator (M) for fractional part of feed- back divider. This is concatenated with Denominator MSB, M[15:8]. Bits[31:24], Numerator MSB Byte 1, N[15:8] of the numerator (N) for fractional part of the feed- back divider. This is concatenated with Numerator LSB, N[7:0]. Bits[23:16], Numerator LSB Byte 0, N[7:0] of the numerator (N) for fractional part of the feed- back divider. This is concatenated with Numerator MSB, N[15:8]. Bits[14:11], Integer Integer (R) parameter used in both integer-N and fractional PLL operation. This value must be between 2 and 8. Bits[10:9], Input Divider The input divider (X) divides the input clock to offer a wider range of input clocks. Bit 8, PLL Type This selects the type of PLL operation, fractional or integer-N. Fractional Type PLL Fractional type MCLK inputs are scaled to the corresponding desired core clock input using the parameters outlined in Table 33 and Table 34 as examples of typical base sampling frequencies (44.1 kHz and 48 kHz). A numerical-controlled oscillator is used to divide the PLL_CLK by a mixed number given by the addition of the integer part (R) and fractional part (N/M). For example, if the MCLK is 12 MHz, the required clock is 12.288 MHz, and fS is 48 kHz, then the PLL clock is 49.152 MHz because PLL clock is always 1024 × fS; therefore, PLL Clock/MCLK = 4.096 = 4 + (12/125) = R + (N/M) In this case, the input divider is X = 1. This allows the MCLK input to emulate the desired required clock and output a 49.152 MHz PLL clock. Figure 30 shows how the PLL uses the parameters to emulate the required 12.288 MHz clock. Integer-N Type PLL Integer-N type MCLK inputs are any integer multiple of the desired core clock. The fractional part (N/M) is 0; however, the PLL type bit must be set for integer-N. Bit 1, PLL Lock The PLL lock bit is a read-only bit. Reading a 1 from this bit indicates that the PLL has locked to the input master clock. Bit 0, PLL Enable This bit enables the PLL. Table 31. Regulator Control Register Bits Description Default [7:3] Reserved [2:1] Regulator output level 01 00: 1.5 V 01: 1.4 V 10: 1.6 V 11: 1.7 V 0 Reserved |
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