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ADAU1381BCPZ Datasheet(PDF) 25 Page - Analog Devices |
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ADAU1381BCPZ Datasheet(HTML) 25 Page - Analog Devices |
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25 / 84 page  ADAU1381 Rev. 0| Page 25 of 84 STARTUP, INITIALIZATION, AND POWER This section details the procedure for setting up the ADAU1381 properly. Figure 27 provides an overview of how to initialize the IC. START CONFIGURE CLOCK GENERATION REGISTER 16384 (0x4000) AND REGISTER 16386 (0x4002) SUPPLY POWER TO AVDD1/AVDD2 PINS SIMULTANEOUSLY SET UP SOUND ENGINE REGISTERS FOR CUSTOMIZED SIGNAL PATH (INCLUDING VOLUME, SAMPLE RATES, FILTER COEFFICIENTS) INITIALIZATION COMPLETE WAIT 14ms FOR POWER-ON RESET AND INITIALIZATION ROM BOOT SUPPLY POWER TO IOVDD ENABLE DIGITAL POWER TO FUNCTIONAL SUBSYSTEMS REGISTER 16512 (0x4080) AND REGISTER 16513 (0x4081) WAIT FOR PLL LOCK (2.4ms TO 3.5ms) ARE AVDD1 AND AVDD2 SUPPLIED SEPARATELY? CAN AVDD1 AND AVDD2 BE SIMULTANEOUSLY SUPPLIED? SUPPLY POWER TO AVDD2 SUPPLY POWER TO AVDD1 NO YES YES NO Figure 27. Initialization Sequence POWER-UP SEQUENCE If AVDD1 and AVDD2 are from the same supply, they can power up simultaneously. If AVDD1 and AVDD2 are from separate supplies, then AVDD1 should be powered up first. IOVDD should be applied simultaneously with AVDD1, if possible. The ADAU1381 uses a power-on reset (POR) circuit to reset the registers upon power-up. The POR monitors the DVDDOUT pin and generates a reset signal whenever power is applied to the chip. During the reset, the ADAU1381 is set to the default values documented in the register map (see the Control Register Map section). The POR is also used to prevent clicks and pops on the speaker driver output. The power-up sequencing and timing involved is described in Figure 28 in this section, and in Figure 36 and Figure 37 of the Speaker Output section. A self-boot ROM initializes the memories after the POR has completed. When the self-boot sequence is complete, the control registers are accessible via the I2C/SPI control port and should then be configured as required for the application. Typically, with a 10 μF capacitor on AVDD1, the power supply ramp-up, POR, and self-boot combined take approximately 14 ms. AVDD1 AVDD2 DVDDOUT POWER-UP (INTERNAL SIGNAL) INTERNAL MCLK (NOT TO SCALE) IOVDD INPUT/OUTPUT PINS ACTIVE 1.35V 1.5V 0.95V MAIN SUPPLY ENABLED POR ACTIVE 1.5V MAIN SUPPLY DISABLED 14ms HIGH-Z HIGH-Z POR COMPLETE/SELF-BOOT INITIATES SELF-BOOT COMPLETE/MEMORY IS ACCESSIBLE POR ACTIVATES Figure 28. Power-Up and Power-Down Sequence Timing Diagram |
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